Document
smu @ MCS@51 8-BIT CONTROL-ORIENTED MICROCONTROLLERS Commercial/Express
8031AH18051AH18051AHP 8032N+18052N-I 8751W8751H-8 8751BW8752BI-I
s High Performance HMOS Process
s Boolean Processor
s Internal Timers/Event Counters
s Bit-Addressable RAM
s 2-Level interrupt Priority Structure
s 32 1/0 Lines (Four 8-Bit Ports)
s 64K External Program Memory Space
s Security Feature Protects EPROM Parts Against Software Piracy
s Programmable Full Duplex Serial Channel
s 111 Instructions (64 Single-Cycle)
s 64K External Data Memory Space s Extended Temperature Range
(–40”C to +85”C)
The MCS@51 controllers are optimized for control applications. Byte-processing and numerical operations on small data structures are facilitated by a variety of fast addressing modes for accessing the internal RAM. The instruction set provides a convenient menu of 8-bit arithmetic instructions, including multiply and divide instructions. Extensive on-chip support is provided for one-bit variables as a separate data type, allowing direct bit manipulation and testing in control and logic systems that require Boolean processing.
The 8751H is an EPROM version of the 8051AH. It has 4 Kbytes of electrically programmable ROM which can be erased with ultraviolet light. His fully compatible with the 8051AH but incorporates one additional feature: a Program Memory Security bit that can be used to protect the EPROM against unauthorized readout. The 8751 H-8 is identical to the 8751 H but only operates up to 8 MHz.
The 8051AHP is identical to the 8051AH with the exception of the Protection Feature. To incorporate this Protection Feature, program verification has been disabled and external memory accesses have been limited to 4K.
The 8052AH is an enhanced version of the 8051AH. It is backwards compatible with the 8051AH and is fabricated with HMOS II technology. The 8052AH enhancements are listed in the table below. Also refer to this table for the ROM, ROMless and-EPROM versions of each product.
Device
8031AH 8051AH 6051AHP 8751 H 8751 H-8 6751 BH 8032AH 6052AH 8752BH
Intsrnal Memory
Program
Data
none 4K X 8 ROM 4K X 6 ROM 4K X 8 EPROM 4K X 8 EPROM 4K X 8 EPROM none 8K X 8 ROM 8K X 8 EPROM
128 X 8 RAM 128 X 8 RAM 128 X 8 RAM 128 X 8 RAM 128 X 6 RAM 128 X 8 RAM 256 X 6 RAM 256 X 8 RAM 256 X 8 RAM
Timera/ Event Counters
2 x 18-Bit 2 x 16-Bit 2 x 16-Bit 2 x 16-Bit 2 x 16-Bit 2 x 16-Bit 3 x 16-Bit 3 x 16-Bit 3 x 16-Bit
Interrupts
5 5 5 5 5 5 6 6 6
I Intel Corporationassumes no responsibilityfor the use of any circuit~ other than circuitryembodied in an Intel product.No other circuitpatent
licenses are implied.Informationcontained herein supersedes previouslypublishedspecificationson theaa davices from Intel.
O INTEL CORPORATION, 1994
October 1994
Order Numben 272318-002
MCS” 51 CONTROLLER
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272318-1
Figure 1. MCSI@51 Controller Block Diagram
PROCESS INFORMATION
The 8031AH/8051AH and 8032AH/8052AH devices are manufactured on P414.1, an HMOS II process. The 8751H/8751 H-8 devices are manufactured on P421.X, an HMOS-E process. The 8751BH and 8752BH devices are manufactured on P422. Additional process and reliability information is available in Intel’s ComponentQsuality and Reliability Handbook, Order No, 210997.
MCS@ 51 CONTROLLER
PACKAGES
Part
8051AH 8031 AH 8052AH 8032AH 6752BH* 8751 H 8751 H-8 8051AHP
8751 BH
Prefix P D N
D
P D P N
Package Type 40-Pin Plastic DIP 40-Pin CERDIP 44-Pin PLCC
40-Pin CERDIP
40-Pin Plastic DIP 40-Pin CERDIP 40-Pin Plastic DIP 44-Pin PLCC
‘ja
45°chV 4!5”CIW 46°C/W
45”CIW
45”CIW 45°c/w 36”CIW 47”C1W
Ojc
16“C/W 15“CAIV 18°CfW
45“CIW
16°Cf W 15“cf w 12°cf w 16”Cf W
NOTE: *8752BHis 36”/10” for D, and 38”/22” for N.
All thermal impedance data is approximate for static air conditions at IW of power dissipation. Values will change depending on operating conditions and application. See the Intel Pac/raging Handbook (Order Number 240800) for a description of Intel’s thermal impedance test methodology.
~“52’80320NL’ ~
T2
L { I’__”llT2EX
PI.’ P1.1 P1.2 P1.3 P1.4 P1.5 P1,6
1 2 3 4 5 6 7
40 Vcc 39 P’,’ ADO 38 PO.1AD1 37 PO.2A02 36 PO.3 A03
35 PO.4AD4
34 PO.5AD5
PI.6 ::8:;
P1.7 6
33 P06 AD’
‘1RST
RU2 P3.O TXD P3.1 INTO P3.2 INT1 P3,3
TOP3 4 11 P3.5 ~ P3.6 t% P3.7
9 10 11 12 13 14 15 16 17
3 PO.7A07
3 EIJvpp” Z ALEIPROG”
29 3%FFI
26 3 P2.7 A15
27 2 P2.6A14
26 3 P2.5 A13 25 I P2.4 A12 24 1 P2.3 Al 1
XTAL2 16
23 > P2.2 AlO
P*,7 .:,.: RST io; (Rxo) P3.O :ji: neaslvsd** .1:; fTXD) P3.1 :ji; (INTo) P3.2 :!;; (INT1) P3.3 :j:; fTo) P3.4 :>!:
8X5X
+!--XTAL1 19 ‘ss
22 3 P2 1 A9 21 X P20 A8
DIP qEPROM only “*Do not connect reserved pins.
PLCC
Figure 2. MCS@51 Controller Connections
272318-2
3
MCS” 51 C.