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80960CA-33 Dataheets PDF



Part Number 80960CA-33
Manufacturers Intel Corporation
Logo Intel Corporation
Description 80960CA-33/ -25/ -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR
Datasheet 80960CA-33 Datasheet80960CA-33 Datasheet (PDF)

80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR • Two Instructions/Clock Sustained Execution • Four 59 Mbytes/s DMA Channels with Data Chaining • Demultiplexed 32-bit Burst Bus with Pipelining s 32-bit Parallel Architecture s Four On-Chip DMA Channels s s s s — Two Instructions/clock Execution — Load/Store Architecture — Sixteen 32-bit Global Registers — Sixteen 32-bit Local Registers — Manipulates 64-bit Bit Fields — 11 Addressing Modes — Full Parallel Fault Model — Supervis.

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80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR • Two Instructions/Clock Sustained Execution • Four 59 Mbytes/s DMA Channels with Data Chaining • Demultiplexed 32-bit Burst Bus with Pipelining s 32-bit Parallel Architecture s Four On-Chip DMA Channels s s s s — Two Instructions/clock Execution — Load/Store Architecture — Sixteen 32-bit Global Registers — Sixteen 32-bit Local Registers — Manipulates 64-bit Bit Fields — 11 Addressing Modes — Full Parallel Fault Model — Supervisor Protection Model Fast Procedure Call/Return Model — Full Procedure Call in 4 Clocks On-Chip Register Cache — Caches Registers on Call/Ret — Minimum of 6 Frames Provided — Up to 15 Programmable Frames On-Chip Instruction Cache — 1 Kbyte Two-Way Set Associative — 128-bit Path to Instruction Sequencer — Cache-Lock Modes — Cache-Off Mode High Bandwidth On-Chip Data RAM — 1 Kbyte On-Chip Data RAM — Sustains 128 bits per Clock Access — 59 Mbytes/s Fly-by Transfers — 32 Mbytes/s Two-Cycle Transfers — Data Chaining — Data Packing/Unpacking — Programmable Priority Method s 32-Bit Demultiplexed Burst Bus — 128-bit Internal Data Paths to and from Registers — Burst Bus for DRAM Interfacing — Address Pipelining Option — Fully Programmable Wait States — Supports 8-, 16- or 32-bit Bus Widths — Supports Unaligned Accesses — Supervisor Protection Pin s Selectable Big or Little Endian Byte Ordering s High-Speed Interrupt Controller — — — — — — Up to 248 External Interrupts 32 Fully Programmable Priorities Multi-mode 8-bit Interrupt Port Four Internal DMA Interrupts Separate, Non-maskable Interrupt Pin Context Switch in 750 ns Typical Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel. © INTEL CORPORATION, 1993 November 1993 Order Number: 270727-006 80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR CONTENTS PAGE 1.0 PURPOSE .................................................................................................................................................. 1 2.0 80960CA OVERVIEW ................................................................................................................................. 1 2.1 The C-Series Core ..............................................................................................................................2 2.2 Pipelined, Burst Bus ...........................................................................................................................2 2.3 Flexible DMA Controller ......................................................................................................................2 2.4 Priority Interrupt Controller ..................................................................................................................2 2.5 Instruction Set Summary ....................................................................................................................3 3.0 PACKAGE INFORMATION .........................................................................................................................4 3.1 Package Introduction ..........................................................................................................................4 3.2 Pin Descriptions .................................................................................................................................. 4 3.3 80960CA Mechanical Data ............................................................................................................... 11 3.3.1 80960CA PGA Pinout ............................................................................................................ 11 3.3.2 80960CA PQFP Pinout .......................................................................................................... 15 3.4 Package Thermal Specifications ...................................................................................................... 18 3.5 Stepping Register Information .......................................................................................................... 20 3.6 Suggested Sources for 80960CA Accessories.................................................................................. 20 4.0 ELECTRICAL SPECIFICATIONS ............................................................................................................. 21 4.1 Absolute Maximum Ratings .............................................................................................................. 21 4.2 Operating Conditions ........................................................................................................................ 21 4.3 Recommended Connections ............................................................................................................ 21 4.4 DC Specifications ....


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