80960CF-16

A www.DataSheet4U.com PRELIMINARY 80960CF-40, -33, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR EMBEDDED MICROPROCESSOR Socket and Object Code Compatible with 80960CA Two Instructions/Clock Sustained Execution Four 71 Mbytes/s DMA Channels with Data Chaining Demultiplexed 32-Bit Burst Bus with Pipelining 32-Bit Parallel Architecture s Four On-Chip DMA Channels — Two Instructions/clock Execution — 71 Mbytes/s Fly-by Transfers — Load/Store Architecture — 40 Mbytes/s Two-Cycle Transfers — Sixteen 32-Bit Global Registers — Data Chaining — Sixteen 32-Bit Local Registers — Data Packing/Unpacking — Manipulates 64-Bit Bit Fields — Programmable Priority Method — 11 Addressing Modes s 32-Bit Demultiplexed Burst Bus — Full Parallel Fault Model — 128-Bit Internal Data Paths to and from — Supervisor Protection Model Registers Fast Procedure Call/Return Model — Burst Bus for DRAM Interfacing — Address Pipelining Option — Full Procedure Call in 4 Clocks — Fully Programmable Wait States On-Chip Register Cache — Supports 8-, 16- or 32-Bit Bus Widths — Caches Registers on Call/Ret — Supports Unaligned Accesses — Minimum of 6 Frames Provided — Supervisor Protection Pin — Up to 15 Programmable Frames s High-Speed Interrupt Controller On-Chip Instruction Cache — Up to 248 External Interrupts — 4 Kbyte Two-Way Set Associative — 32 Fully Programmable Priorities — 128-Bit Path to Instruction Sequencer — Multi-mode 8-Bit Interrupt Port — Cache-Lock Modes — Four Internal DMA Interrupts — Ca...