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80960CF-25 Dataheets PDF



Part Number 80960CF-25
Manufacturers Intel Corporation
Logo Intel Corporation
Description SPECIAL ENVIRONMENT 80960CF-30/ -25/ -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR
Datasheet 80960CF-25 Datasheet80960CF-25 Datasheet (PDF)

A www.DataSheet4U.com PRELIMINARY 80960CF-40, -33, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR EMBEDDED MICROPROCESSOR • Socket and Object Code Compatible with 80960CA • Two Instructions/Clock Sustained Execution • Four 71 Mbytes/s DMA Channels with Data Chaining • Demultiplexed 32-Bit Burst Bus with Pipelining 32-Bit Parallel Architecture s Four On-Chip DMA Channels — Two Instructions/clock Execution — 71 Mbytes/s Fly-by Transfers — Load/Store Architecture — 40 Mbytes/s Two-Cycle Transfers .

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A www.DataSheet4U.com PRELIMINARY 80960CF-40, -33, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR EMBEDDED MICROPROCESSOR • Socket and Object Code Compatible with 80960CA • Two Instructions/Clock Sustained Execution • Four 71 Mbytes/s DMA Channels with Data Chaining • Demultiplexed 32-Bit Burst Bus with Pipelining 32-Bit Parallel Architecture s Four On-Chip DMA Channels — Two Instructions/clock Execution — 71 Mbytes/s Fly-by Transfers — Load/Store Architecture — 40 Mbytes/s Two-Cycle Transfers — Sixteen 32-Bit Global Registers — Data Chaining — Sixteen 32-Bit Local Registers — Data Packing/Unpacking — Manipulates 64-Bit Bit Fields — Programmable Priority Method — 11 Addressing Modes s 32-Bit Demultiplexed Burst Bus — Full Parallel Fault Model — 128-Bit Internal Data Paths to and from — Supervisor Protection Model Registers Fast Procedure Call/Return Model — Burst Bus for DRAM Interfacing — Address Pipelining Option — Full Procedure Call in 4 Clocks — Fully Programmable Wait States On-Chip Register Cache — Supports 8-, 16- or 32-Bit Bus Widths — Caches Registers on Call/Ret — Supports Unaligned Accesses — Minimum of 6 Frames Provided — Supervisor Protection Pin — Up to 15 Programmable Frames s High-Speed Interrupt Controller On-Chip Instruction Cache — Up to 248 External Interrupts — 4 Kbyte Two-Way Set Associative — 32 Fully Programmable Priorities — 128-Bit Path to Instruction Sequencer — Multi-mode 8-Bit Interrupt Port — Cache-Lock Modes — Four Internal DMA Interrupts — Cache-Off Mode — Separate, Non-maskable Interrupt Pin High Bandwidth On-Chip Data RAM — Context Switch in 625 ns Typical — 1 Kbyte On-Chip Data RAM s On-Chip Data Cache — Sustains 128 bits per Clock Access — 1 Kbyte Direct-Mapped, Write Through Selectable Big or Little Endian Byte — 128 bits per Clock Access on Cache Hit Ordering s s s s s s © INTEL CORPORATION, 1996 June 1996 Order Number: 272886-001 www.DataSheet4U.com Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel retains the right to make changes to specifications and product descriptions at any time, without notice. *Third-party brands and names are the property of their respective owners. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect IL 60056-764 or call 1-800-548-4725 www.DataSheet4U.com A 80960CF-40, -33, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR EMBEDDED MICROPROCESSOR CONTENTS 1.0 PURPOSE .................................................................................................................................................. 1 2.0 80960CF OVERVIEW ................................................................................................................................ 1 2.1 The 80960C-Series Core .................................................................................................................... 3 2.2 Pipelined, Burst Bus ........................................................................................................................... 3 2.3 Instruction Set Summary .................................................................................................................... 3 2.4 Flexible DMA Controller ...................................................................................................................... 3 2.5 Priority Interrupt Controller .................................................................................................................. 4 3.0 PACKAGE INFORMATION ........................................................................................................................ 5 3.1 Package Introduction .......................................................................................................................... 5 3.2 Pin Descriptions .................................................................................................................................. 5 3.3 80960CF Mechanical Data ............................................................................................................... 12 3.3.1 80960CF PGA PINOUT ......................................................................................................... 12 3.3.2 80960CF PQFP Pinout (80960CF-33, -25, -16 Only) ...............


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