MICROPROCESSOR. 80960JA Datasheet

80960JA Datasheet PDF


Part

80960JA

Description

EMBEDDED 32-BIT MICROPROCESSOR

Manufacture

Intel Corporation

Page 30 Pages
Datasheet
Download 80960JA Datasheet


80960JA Datasheet
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A
PRELIMINARY
80960JA/JF
EMBEDDED 32-BIT MICROPROCESSOR
s Pin/Code Compatible with all 80960Jx
Processors
s High-Performance Embedded Architecture
— One Instruction/Clock Execution
— Load/Store Programming Model
— Sixteen 32-Bit Global Registers
— Sixteen 32-Bit Local Registers (8 sets)
— Nine Addressing Modes
— User/Supervisor Protection Model
s High Bandwidth Burst Bus
— 32-Bit Multiplexed Address/Data
— Programmable Memory Configuration
— Selectable 8-, 16-, 32-Bit Bus Widths
— Supports Unaligned Accesses
— Big or Little Endian Byte Ordering
s New Instructions
— Conditional Add, Subtract and Select
— Processor Management
s Two-Way Set Associative Instruction Cache s High-Speed Interrupt Controller
— 80960JA - 2 Kbyte
— 80960JF - 4 Kbyte
— Programmable Cache Locking
— 31 Programmable Priorities
— Eight Maskable Pins plus NMI
— Up to 240 Vectors in Expanded Mode
Mechanism
s Two On-Chip Timers
s Direct Mapped Data Cache
— Independent 32-Bit Counting
— 80960JA - 1 Kbyte
— 80960JF - 2 Kbyte
— Clock Prescaling by 1, 2, 4 or 8
— lnternal Interrupt Sources
— Write Through Operation
s Halt Mode for Low Power
s On-Chip Stack Frame Cache
— Seven Register Sets Can Be Saved
— Automatic Allocation on Call/Return
s IEEE 1149.1 (JTAG) Boundary Scan
Compatibility
— 0-7 Frames Reserved for High-Priority s Packages
Interrupts
— 132-Lead Pin Grid Array (PGA)
s On-Chip Data RAM
— 132-Lead Plastic Quad Flat Pack (PQFP)
— 1 Kbyte Critical Variable Storage
— Single-Cycle Access
iA80960Jx
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M © 19xx
PIN 1
132
33
A
i960®
iNG80960Jx
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M © 19xx
99
66
Figure 1. 80960JA/JF Microprocessors
Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any
patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Information
contained herein supersedes previously published specifications on these devices from Intel.
© INTEL CORPORATION, 1995
September 1995
Order Number: 272504-004

80960JA Datasheet
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A
80960JA/JF
80960JA/JF
EMBEDDED 32-BIT MICROPROCESSOR
1.0 PURPOSE ..................................................................................................................................................1
2.0 80960JA/JF OVERVIEW ............................................................................................................................1
2.1 80960 Processor Core ........................................................................................................................2
2.2 Burst Bus ............................................................................................................................................2
2.3 Timer Unit ...........................................................................................................................................3
2.4 Priority Interrupt Controller .................................................................................................................3
2.5 Instruction Set Summary ....................................................................................................................3
2.6 Faults and Debugging .........................................................................................................................3
2.7 Low Power Operation .........................................................................................................................4
2.8 Test Features ......................................................................................................................................4
2.9 Memory-Mapped Control Registers ....................................................................................................4
2.10 Data Types and Memory Addressing Modes ....................................................................................4
3.0 PACKAGE INFORMATION ........................................................................................................................6
3.1 Pin Descriptions ..................................................................................................................................6
3.1.1 Functional Pin Definitions ........................................................................................................6
3.1.2 80960Jx 132-Lead PGA Pinout .............................................................................................13
3.1.3 80960Jx PQFP Pinout ...........................................................................................................17
3.2 Package Thermal Specifications ......................................................................................................20
4.0 ELECTRICAL SPECIFICATIONS ............................................................................................................22
4.1 Absolute Maximum Ratings ..............................................................................................................22
4.2 Operating Conditions ........................................................................................................................22
4.3 Connection Recommendations .........................................................................................................22
4.4 DC Specifications .............................................................................................................................23
4.5 AC Specifications ..............................................................................................................................25
4.5.1 AC Test Conditions and Derating Curves ...............................................................................32
4.5.2 AC Timing Waveforms ............................................................................................................33
5.0 BUS FUNCTIONAL WAVEFORMS .........................................................................................................41
6.0 DEVICE IDENTIFICATION .......................................................................................................................55
7.0 REVISION HISTORY ...............................................................................................................................55
PRELIMINARY
ii


Features Datasheet pdf www.DataSheet4U.com A s s PRELIMINARY 80960JA/JF EMBEDDED 32-BIT MICROPROCES SOR Pin/Code Compatible with all 80960J x Processors High-Performance Embedded Architecture — One Instruction/Clock Execution — Load/Store Programming Mo del — Sixteen 32-Bit Global Registers — Sixteen 32-Bit Local Registers (8 sets) — Nine Addressing Modes — Use r/Supervisor Protection Model Two-Way S et Associative Instruction Cache — 80 960JA - 2 Kbyte — 80960JF - 4 Kbyte Programmable Cache Locking Mechanism Direct Mapped Data Cache — 80960JA - 1 Kbyte — 80960JF - 2 Kbyte — Writ e Through Operation On-Chip Stack Frame Cache — Seven Register Sets Can Be S aved — Automatic Allocation on Call/R eturn — 0-7 Frames Reserved for High- Priority Interrupts On-Chip Data RAM 1 Kbyte Critical Variable Storage — Single-Cycle Access s High Bandwidth B urst Bus s s s s s s — 32-Bit Multiplexed Address/Data — Programmab le Memory Configuration — Selectable 8-, 16-, 32-Bit Bus Widths — Supports Unaligned Accesses — Big o.
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