32-BIT MICROPROCESSOR. 80960JD Datasheet

80960JD Datasheet PDF, Equivalent


Part Number

80960JD

Description

EMBEDDED 32-BIT MICROPROCESSOR

Manufacture

Intel Corporation

Total Page 30 Pages
PDF Download
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80960JD Datasheet
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A
PRELIMINARY
80960JD
EMBEDDED 32-BIT MICROPROCESSOR
s Pin/Code Compatible with all 80960Jx
s High Bandwidth Burst Bus
Processors
— 32-Bit Multiplexed Address/Data
s High-Performance Embedded Architecture
— One Instruction/Clock Execution
— Core Clock Rate is 2x the Bus Clock
— Load/Store Programming Model
— Sixteen 32-Bit Global Registers
— Sixteen 32-Bit Local Registers (8 sets)
— Nine Addressing Modes
— Programmable Memory Configuration
— Selectable 8-, 16-, 32-Bit Bus Widths
— Supports Unaligned Accesses
— Big or Little Endian Byte Ordering
s New Instructions
— Conditional Add, Subtract and Select
— Processor Management
— User/Supervisor Protection Model
s High-Speed Interrupt Controller
s Two-Way Set Associative Instruction Cache — 31 Programmable Priorities
— 80960JD - 4 Kbyte
— Programmable Cache Locking
— Eight Maskable Pins plus NMI
— Up to 240 Vectors in Expanded Mode
Mechanism
s Two On-Chip Timers
s Direct Mapped Data Cache
— Independent 32-Bit Counting
— 80960JD - 2 Kbyte
— Write Through Operation
— Clock Prescaling by 1, 2, 4 or 8
— lnternal Interrupt Sources
s On-Chip Stack Frame Cache
— Seven Register Sets Can Be Saved
— Automatic Allocation on Call/Return
— 0-7 Frames Reserved for High-Priority
Interrupts
s On-Chip Data RAM
— 1 Kbyte Critical Variable Storage
— Single-Cycle Access
s Halt Mode for Low Power
s IEEE 1149.1 (JTAG) Boundary Scan
Compatibility
s Packages
— 132-Lead Pin Grid Array (PGA)
— 132-Lead Plastic Quad Flat Pack (PQFP)
iA80960JD
XXXXXXXXA2
M © 19xx
PIN 1
132
33
A
i960®
iNG80960JD
XXXXXXXXA2
M © 19xx
99
66
Figure 1. 80960JD Microprocessor
Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any
patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Information
contained herein supersedes previously published specifications on these devices from Intel.
© INTEL CORPORATION, 1995
September 1995
Order Number: 272596-002

80960JD Datasheet
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A
80960JD
80960JD
EMBEDDED 32-BIT MICROPROCESSOR
1.0 PURPOSE ..................................................................................................................................................1
2.0 80960JD OVERVIEW ................................................................................................................................. 1
2.1 80960 Processor Core ........................................................................................................................2
2.2 Burst Bus ............................................................................................................................................2
2.3 Timer Unit ...........................................................................................................................................3
2.4 Priority Interrupt Controller .................................................................................................................3
2.5 Instruction Set Summary ....................................................................................................................3
2.6 Faults and Debugging .........................................................................................................................3
2.7 Low Power Operation .........................................................................................................................4
2.8 Test Features ......................................................................................................................................4
2.9 Memory-Mapped Control Registers ....................................................................................................4
2.10 Data Types and Memory Addressing Modes ....................................................................................4
3.0 PACKAGE INFORMATION ........................................................................................................................6
3.1 Pin Descriptions ..................................................................................................................................6
3.1.1 Functional Pin Definitions ........................................................................................................6
3.1.2 80960Jx 132-Lead PGA Pinout .............................................................................................13
3.1.3 80960Jx PQFP Pinout ...........................................................................................................17
3.2 Package Thermal Specifications ......................................................................................................20
3.3 Thermal Management Accessories ..................................................................................................22
4.0 ELECTRICAL SPECIFICATIONS ............................................................................................................23
4.1 Absolute Maximum Ratings ..............................................................................................................23
4.2 Operating Conditions ........................................................................................................................23
4.3 Connection Recommendations .........................................................................................................24
4.4 DC Specifications .............................................................................................................................24
4.5 AC Specifications ..............................................................................................................................26
4.5.1 AC Test Conditions and Derating Curves ...............................................................................33
4.5.2 AC Timing Waveforms ............................................................................................................34
5.0 BUS FUNCTIONAL WAVEFORMS .........................................................................................................42
6.0 DEVICE IDENTIFICATION .......................................................................................................................56
7.0 REVISION HISTORY ...............................................................................................................................56
PRELIMINARY
ii


Features Datasheet pdf www.DataSheet4U.com A s s PRELIMINARY 80960JD EMBEDDED 32-BIT MICROPROCESSOR Pin/Code Compatible with all 80960Jx P rocessors High-Performance Embedded Arc hitecture — One Instruction/Clock Exe cution — Core Clock Rate is 2x the Bu s Clock — Load/Store Programming Mode l — Sixteen 32-Bit Global Registers Sixteen 32-Bit Local Registers (8 se ts) — Nine Addressing Modes — User/ Supervisor Protection Model Two-Way Set Associative Instruction Cache — 8096 0JD - 4 Kbyte — Programmable Cache Lo cking Mechanism Direct Mapped Data Cach e — 80960JD - 2 Kbyte — Write Throu gh Operation On-Chip Stack Frame Cache — Seven Register Sets Can Be Saved Automatic Allocation on Call/Return 0-7 Frames Reserved for High-Priorit y Interrupts On-Chip Data RAM — 1 Kby te Critical Variable Storage — Single -Cycle Access s High Bandwidth Burst Bu s s s s s s s s — 32-Bit Mult iplexed Address/Data — Programmable M emory Configuration — Selectable 8-, 16-, 32-Bit Bus Widths — Supports Unaligned Accesses — Big or .
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