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80960SA Dataheets PDF



Part Number 80960SA
Manufacturers Intel Corporation
Logo Intel Corporation
Description EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS
Datasheet 80960SA Datasheet80960SA Datasheet (PDF)

80960SA EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS s High-Performance Embedded s Pin Compatible with 80960SB s Built-in Interrupt Controller Architecture — 20 MIPS* Burst Execution at 20 MHz — 7.5 MIPS Sustained Execution at 20 MHz s 512-Byte On-Chip Instruction Cache — Direct Mapped — Parallel Load/Decode for Uncached Instructions s Multiple Register Sets — Sixteen Global 32-Bit Registers — Sixteen Local 32-Bit Registers — Four Local Register Sets Stored On-Chip — Register Score.

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80960SA EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS s High-Performance Embedded s Pin Compatible with 80960SB s Built-in Interrupt Controller Architecture — 20 MIPS* Burst Execution at 20 MHz — 7.5 MIPS Sustained Execution at 20 MHz s 512-Byte On-Chip Instruction Cache — Direct Mapped — Parallel Load/Decode for Uncached Instructions s Multiple Register Sets — Sixteen Global 32-Bit Registers — Sixteen Local 32-Bit Registers — Four Local Register Sets Stored On-Chip — Register Scoreboarding — 4 Direct Interrupt Pins — 31 Priority Levels, 256 Vectors s Easy to Use, High Bandwidth 16-Bit Bus — 32 Mbytes/s Burst — Up to 16 Bytes Transferred per Burst s 32-Bit Address Space, 4 Gigabytes s 80-Lead Quad Flat Pack (EIAJ QFP) — 84-Lead Plastic Leaded Chip Carrier (PLCC) s Software Compatible with 80960KA/KB/CA/CF Processors The 80960SA is a member of Intel’s i960® 32-bit processor family, which is designed especially for low cost embedded applications. It includes a 512-byte instruction cache and a built-in interrupt controller. The 80960SA has a large register set, multiple parallel execution units and a 16-bit burst bus. Using advanced RISC technology, this high performance processor is capable of execution rates in excess of 7.5 million instructions per second*. The 80960SA is well-suited for a wide range of cost sensitive embedded applications including non-impact printers, network adapters and I/O controllers. 64- BY 32-BIT LOCAL REGISTER CACHE 32-BIT INSTRUCTION EXECUTION UNIT SIXTEEN 32-BIT GLOBAL REGISTERS INSTRUCTION FETCH UNIT 512-BYTE INSTRUCTION CACHE INSTRUCTION DECODER MICROINSTRUCTION SEQUENCER MICROINSTRUCTION ROM 32-BIT BUS CONTROL LOGIC 32-BIT ADDRESS 16-BIT BURST BUS Figure 1. The 80960SA Processor’s Highly Parallel Architecture * Relative to Digital Equipment Corporation’s VAX-11/780 at 1 MIPS (VAX-11™ is a trademark of Digital Equipment Corporation) Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel. © INTEL CORPORATION, 1993 November 1993 Order Number: 272206-002 80960SA EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS CONTENTS PAGE 1.0 THE i960 ® PROCESSOR ...........................................................................................................................1 1.1 Key Performance Features .................................................................................................................2 1.1.1 Memory Space And Addressing Modes ................................................................................... 4 1.1.2 Data Types ...............................................................................................................................4 1.1.3 Large Register Set ...................................................................................................................4 1.1.4 Multiple Register Sets ..............................................................................................................5 1.1.5 Instruction Cache .....................................................................................................................6 1.1.6 Register Scoreboarding ........................................................................................................... 6 1.1.7 High Bandwidth Bus ................................................................................................................6 1.1.8 Interrupt Handling ....................................................................................................................6 1.1.9 Debug Features .......................................................................................................................6 1.1.10 Fault Detection .......................................................................................................................7 1.1.11 Built-in Testability ....................................................................................................................7 1.1.12 CHMOS .................................................................................................................................. 7 2.0 ELECTRICAL SPECIFICATIONS ............................................................................................................. 11 2.1 Power and Grounding ....................................................................................................................... 11 2.2 Power Decoupling Recommendations .............................................................................................. 11 2.3 Connection Recommendations ......................................................................................................... 11 2.4 Characteristic Curves .............................................................................


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