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80C166 Dataheets PDF



Part Number 80C166
Manufacturers Siemens Semiconductor Group
Logo Siemens Semiconductor Group
Description 16-Bit CMOS Single-Chip Microcontroller
Datasheet 80C166 Datasheet80C166 Datasheet (PDF)

Microcomputer Components 16-Bit CMOS Single-Chip Microcontroller SAB 80C166/83C166 Data Sheet 09.94 C16x-Family of High-Performance CMOS 16-Bit Microcontrollers Preliminary SAB 80C166/83C166 SAB 80C166/83C166 16-Bit Microcontroller q q q q q q q q q q q q q q q q q q q q q q q q q q High Performance 16-bit CPU with 4-Stage Pipeline 100 ns Instruction Cycle Time at 20 MHz CPU Clock 500 ns Multiplication (16 × 16 bit), 1 µs Division (32 / 16 bit) Enhanced Boolean Bit Manipulation Facilitie.

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Microcomputer Components 16-Bit CMOS Single-Chip Microcontroller SAB 80C166/83C166 Data Sheet 09.94 C16x-Family of High-Performance CMOS 16-Bit Microcontrollers Preliminary SAB 80C166/83C166 SAB 80C166/83C166 16-Bit Microcontroller q q q q q q q q q q q q q q q q q q q q q q q q q q High Performance 16-bit CPU with 4-Stage Pipeline 100 ns Instruction Cycle Time at 20 MHz CPU Clock 500 ns Multiplication (16 × 16 bit), 1 µs Division (32 / 16 bit) Enhanced Boolean Bit Manipulation Facilities Register-Based Design with Multiple Variable Register Banks Single-Cycle Context Switching Support Up to 256 KBytes Linear Address Space for Code and Data 1 KByte On-Chip RAM 32 KBytes On-Chip ROM (SAB 83C166 only) Programmable External Bus Characteristics for Different Address Ranges 8-Bit or 16-Bit External Data Bus Multiplexed or Demultiplexed External Address/Data Buses Hold and Hold-Acknowledge Bus Arbitration Support 512 Bytes On-Chip Special Function Register Area Idle and Power Down Modes 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC) 16-Priority-Level Interrupt System 10-Channel 10-bit A/D Converter with 9.7 µs Conversion Time 16-Channel Capture/Compare Unit Two Multi-Functional General Purpose Timer Units with 5 Timers Two Serial Channels (USARTs) Programmable Watchdog Timer Up to 76 General Purpose I/O Lines Supported by a Wealth of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards On-Chip Bootstrap Loader 100-Pin Plastic MQFP Package (EIAJ) Semiconductor Group 1 09.94 SAB 80C166/83C166 Introduction The SAB 80C166 is the first representative of the Siemens SAB 80C166 family of full featured single-chip CMOS microcontrollers. It combines high CPU performance (up to 10 million instructions per second) with high peripheral functionality and enhanced IO-capabilities. SAB 80C166 Figure 1 Logic Symbol Ordering Information Type SAB 83C166-5M Ordering Code Package Q67121-D... Function P-MQFP-100-2 16-bit microcontroller, 0 ˚C to +70 ˚C, 1 KByte RAM and 32 KByte ROM P-MQFP-100-2 16-bit microcontroller, -40 ˚C to +85 ˚C, 1 KByte RAM and 32 KByte ROM P-MQFP-100-2 16-bit microcontroller, 0 ˚C to +70 ˚C 1 KByte RAM P-MQFP-100-2 16-bit microcontroller, -40 ˚C to +85 ˚C 1 KByte RAM SAB 83C166-5M-T3 Q67121-D... SAB 80C166-M SAB 80C166-M-T3 Q67121-C848 Q67121-C900 Note: The ordering codes (Q67120-D...) for the Mask-ROM versions are defined for each product after verification of the respective ROM code. Semiconductor Group 2 SAB 80C166/83C166 Pin Configuration Rectangular P-MQFP-100-2 (top view) SAB 80C166 Figure 2 Semiconductor Group 3 SAB 80C166/83C166 Pin Definitions and Functions Symbol P4.0 – P4.1 Pin Input Number Output 16-17 I/O Function Port 4 is a 2-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. In case of an external bus configuration, Port 4 can be used to output the segment address lines: P4.0 A16 Least Significant Segment Addr. Line P4.1 A17 Most Significant Segment Addr. Line XTAL1: Input to the oscillator amplifier and input to the internal clock generator XTAL2: Output of the oscillator amplifier circuit. To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed. External Bus Configuration selection inputs. These pins are sampled during reset and select either the single chip mode or one of the four external bus configurations: BUSACT EBC1 EBC0 Mode/Bus Configuration 0 0 0 8-bit demultiplexed bus 0 0 1 8-bit multiplexed bus 0 1 0 16-bit multiplexed bus 0 1 1 16-bit demultiplexed bus 1 0 0 Single chip mode 1 0 1 Reserved. 1 1 0 Reserved. 1 1 1 Reserved. ROMless versions must have pin BUSACT tied to ‘0’. Reset Input with Schmitt-Trigger characteristics. A low level at this pin for a specified duration while the oscillator is running resets the SAB 80C166. An internal pullup resistor permits power-on reset using only a capacitor connected to VSS. Internal Reset Indication Output. This pin is set to a low level when the part is executing either a hardware-, a software- or a watchdog timer reset. RSTOUT remains low until the EINIT (end of initialization) instruction is executed. 16 17 XTAL1 XTAL2 20 19 O O I O BUSACT, EBC1, EBC0 22 23 24 I I I RSTIN 27 I RSTOUT 28 O Semiconductor Group 4 SAB 80C166/83C166 Pin Definitions and Functions (cont’d) Symbol NMI Pin Input Number Output 29 I Function Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. When the PWRDN (power down) instruction is executed, pin NMI must be low in order to force the SAB 80C166 to go into power down mode. If NMI.


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