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80C186EB Dataheets PDF



Part Number 80C186EB
Manufacturers Intel Corporation
Logo Intel Corporation
Description 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
Datasheet 80C186EB Datasheet80C186EB Datasheet (PDF)

80C186EB 80C188EB AND 80L186EB 80L188EB 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS X Y X Full Static Operation True CMOS Inputs and Outputs Y Integrated Feature Set Low-Power Static CPU Core Two Independent UARTs each with an Integral Baud Rate Generator Two 8-Bit Multiplexed I O Ports Programmable Interrupt Controller Three Programmable 16-Bit Timer Counters Clock Generator Ten Programmable Chip Selects with Integral Wait-State Generator Memory Refresh Control Unit System Level Testing Suppo.

  80C186EB   80C186EB


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80C186EB 80C188EB AND 80L186EB 80L188EB 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS X Y X Full Static Operation True CMOS Inputs and Outputs Y Integrated Feature Set Low-Power Static CPU Core Two Independent UARTs each with an Integral Baud Rate Generator Two 8-Bit Multiplexed I O Ports Programmable Interrupt Controller Three Programmable 16-Bit Timer Counters Clock Generator Ten Programmable Chip Selects with Integral Wait-State Generator Memory Refresh Control Unit System Level Testing Support (ONCE Mode) Direct Addressing Capability to 1 Mbyte Memory and 64 Kbyte I O Speed Versions Available (5V) 25 MHz (80C186EB25 80C188EB25) 20 MHz (80C186EB20 80C188EB20) 13 MHz (80C186EB13 80C188EB13) Available in Extended Temperature Range ( b 40 C to a 85 C) Speed Versions Available (3V) 16 MHz (80L186EB16 80L188EB16) 13 MHz (80L186EB13 80L188EB13) 8 MHz (80L186EB8 80L188EB8) Low-Power Operating Modes Idle Mode Freezes CPU Clocks but keeps Peripherals Active Powerdown Mode Freezes All Internal Clocks Supports 80C187 Numeric Coprocessor Interface (80C186EB PLCC Only) Available In 80-Pin Quad Flat Pack (QFP) 84-Pin Plastic Leaded Chip Carrier (PLCC) 80-Pin Shrink Quad Flat Pack (SQFP) Y Y Y Y Y Y The 80C186EB is a second generation CHMOS High-Integration microprocessor It has features that are new to the 80C186 family and include a STATIC CPU core an enhanced Chip Select decode unit two independent Serial Channels I O ports and the capability of Idle or Powerdown low power modes 272433 – 1 Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata October 1995 COPYRIGHT INTEL CORPORATION 1995 Order Number 272433-004 1 80C186EB 80C188EB and 80L186EB 80L188EB 16-Bit High-Integration Embedded Processors CONTENTS INTRODUCTION CORE ARCHITECTURE Bus Interface Unit Clock Generator 80C186EC PERIPHERAL ARCHITECTURE Interrupt Control Unit Timer Counter Unit Serial Communications Unit Chip-Select Unit I O Port Unit Refresh Control Unit Power Management Unit 80C187 Interface (80C186EB Only) ONCE Test Mode PACKAGE INFORMATION Prefix Identification Pin Descriptions 80C186EB PINOUT PACKAGE THERMAL SPECIFICATIONS ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings PAGE 4 4 4 4 5 5 5 7 7 7 7 7 7 7 8 8 8 14 22 23 23 CONTENTS Recommended Connections DC SPECIFICATIONS ICC versus Frequency and Voltage PDTMR Pin Delay Calculation AC SPECIFICATIONS AC Characteristics 80C186EB25 AC Characteristics 80C186EB20 13 AC Characteristics 80L186EB16 Relative Timings Serial Port Mode 0 Timings AC TEST CONDITIONS AC TIMING WAVEFORMS DERATING CURVES RESET BUS CYCLE WAVEFORMS EXECUTION TIMINGS INSTRUCTION SET SUMMARY ERRATA REVISION HISTORY PAGE 23 24 27 27 28 28 30 32 36 37 38 38 41 42 45 52 53 59 59 2 2 80C186EB 80C188EB 80L186EB 80L188EB 272433 – 2 NOTE Pin names in parentheses apply to the 80C188EB 80L188EB Figure 1 80C186EB 80C188EB Block Diagram 3 3 80C186EB 80C188EB 80L186EB 80L188EB cept the queue status mode has been deleted and buffer interface control has been changed to ease system design timings An independent internal bus is used to allow communication between the BIU and internal peripherals INTRODUCTION Unless specifically noted all references to the 80C186EB apply to the 80C188EB 80L186EB and 80L188EB References to pins that differ between the 80C186EB 80L186EB and the 80C188EB 80L188EB are given in parentheses The ‘‘L’’ in the part number denotes low voltage operation Physically and functionally the ‘‘C’’ and ‘‘L’’ devices are identical The 80C186EB is the first product in a new generation of low-power high-integration microprocessors It enhances the existing 186 family by offering new features and new operating modes The 80C186EB is object code compatible with the 80C186XL 80C188XL microprocessors The 80L186EB is the 3V version of the 80C186EB The 80L186EB is functionally identical to the 80C186EB embedded processor Current 80C186EB users can easily upgrade their designs to use the 80L186EB and benefit from the reduced power consumption inherent in 3V operation The feature set of the 80C186EB meets the needs of low power space critical applications Low-Power applications benefit from the static design of the CPU core and the integrated peripherals as well as low voltage operation Minimum current consumption is achieved by providing a Powerdown mode that halts operation of the device and freezes the clock circuits Peripheral design enhancements ensure that non-initialized peripherals consume little current Space critical applications benefit from the integratio.


80C186EA 80C186EB 80C186EC


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