MK2308-1

MK2308-1 3.3 VOLT ZERO DELAY, LOW SKEW BUFFER Description The MK2308-1 is a low phase noise, high-speed PLL based, 8-output, low-skew zero delay buffer. Based on ICS’ proprietary low jitter Phase Locked Loop (PLL) techniques, the device provides eight low skew outputs at speeds up to 133 MHz at 3.3 V. The outputs can be generated from the PLL (for zero delay), or directly from the input (for testing), and can be set to tri-state mode or to stop at a low level. For normal operation as a zero delay buffer, any output clock is tied to the FBIN pin. ICS manufactures a variety of clock generators and buffers. Features Clock outputs from 10 to 133 MHz Zero input-output delay Eight low skew (<200 ps) outputs Device-to-device skew <700 ps Full CMOS outputs with 25 mA output drive capability at TTL levels 5 V tolerant FBIN and CLKIN pins Tri-state mode for board-level testing Advanced, low power, sub-micron CMOS process Operating voltage of 3.3 V Industrial temperature range available Packaged in 16-pin SOIC Block Diagram VDD 2 2 Control Logic S2, S1 CLKA1 CLKA2 CLKIN CLKA3 CLKA4 FBIN Clock Synthesis PLL 1 0 CLKB1 CLKB2 CLKB3 CLKB4 GND 2 Feedback is shown from CLKB4 for illustration, but may come from any output. MDS 2308-1 A I n t e gra te d C i r c u i t S y s te m s ● 1 52 5 Ra ce Street, San Jose, CA 9 512 6 ● Revision 100603 tel (408 ) 295 -980 0 ● w ww.i c s t. c om MK2308-1 3.3 VOLT ZERO DELAY, LOW SKEW BUFFER Pin Assignment C L K IN C ...