MK50H25

MK50H25 HIGH SPEED LINK LEVEL CONTROLLER ADVANCE DATA SECTION 1 - FEATURES System clock rate up to 33 MHz (MK50H25 33), 25 MHz (MK50H25 - 25), or 16 MHz (MK50H25 - 16). Data rate up to 20 Mbps continuous (MK50H25 - 33) or up to 51 Mbps bursted On chip DMA control with programmable burst length. DMA transfer rate of up to 13.3 Mbytes/sec using optional 5 SYSCLK DMA cycle (150 nS) at 33 MHz SYSCLK. Complete Level 2 implementation compatible with X.25 LAPB, ISDN LAPD, X.32, and X.75 Protocols. Handles all error recovery, sequencing, and S and U frame control. Pin-for-pin and architecturally compatible with MK5025 (X.25/LAPD), MK5027 (CCS#7) and MK5029(SDLC). Buffer Management includes: - Initialization Block - Separate Receive and Transmit Rings - Variable Descriptor Ring and Window Sizes. Separate 64-byte Transmit and Receive FIFO. Programmable Transmit FIFO hold-off watermark. Handles all HDLC frame formatting: - Zero bit insertion and deletion - FCS (CRC) generation and detection - Frame delimiting with flags Programmable Single or Extended Address and Control fields. Five programmable timer/counters: T1, T3, TP, N1, N2 Programmable minimum frame spacing on transmission (number of flags between frames). - Programmable from 1 to 62 flags between frames Selectable FCS (CRC) of 16 or 32 bits, and passing of entire FCS to buffer. Testing Facilities: - Internal Loopback - Silent Loopback - Optional Internal Data Clock Generation - Self Test. Programmable for full or half duplex o...