ML2021

www.fairchildsemi.com ML2021 Telephone Line Equalizer Features Slope, height, and bandwidth adjustable Optimized group delays (500 Hz to 6.4 kHz) On chip anti-alias filter Bypass mode Low supply current 6 mA typical from ±5V supplies TTL / CMOS compatible interface Double buffered data latch Selectable master clock 1.544 or 1.536 MHz Synchronous or asynchronous data loading capability Compatible with ML2003 and ML2004 logarithmic gain/attenuator General Description The ML2021 is a monolithic analog line equalizer for telephone applications. The ML2021 consists of a switched capacitor filter that realizes a family of frequency response curves optimized for telephone line equalization while minimizing group delay. The ML2021 consists of a continuous anti-aliasing filter, three programmable switched capacitor equalization filters, an output smoothing filter, a 600Ω driver, and a digital section for the serial interface. The equalization filters adjust the slope, height, and bandwidth of the frequency response. The desired frequency response is programmed by a digital 14-bit serial input data stream. Block Diagram CLKSEL VCC AGND VSS Pin Connections ML2021 16-PIN DIP CLKSEL 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC PDN VOUT AGND VIN VSS LATI GND CLK CLOCK GENERATOR SMOOTHING FILTER VOUT SID NC LATO VIN ANTIALIAS LO PASS MUX SCK NC SOD SLOPE SECTION PDN LATI 5 HEIGHT SECTION 4 14-BIT LATCH 14 BANDPASS SECTION 4 1 CLK GND TOP VIEW ML2021 18-PIN S...