Digital CrosspointTM. 80VA Datasheet

80VA Datasheet PDF, Equivalent

Part Number



In-System Programmable 3.3V Generic Digital CrosspointTM


Lattice Semiconductor

Total Page 27 Pages
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80VA Datasheet
In-System Programmable
3.3V Generic Digital CrosspointTM
Functional Block Diagram
— Advanced Architecture Addresses Programmable
PCB Interconnect, Bus Interface Integration and
Jumper/Switch Replacement
— “Any Input to Any Output” Routing
— Fixed HIGH or LOW Output Option for Jumper/DIP
Switch Emulation
— Space-Saving PQFP and BGA Packaging
— Dedicated IEEE 1149.1-Compliant Boundary Scan
— 3.3V Core Power Supply
— 3.5ns Input-to-Output/3.5ns Clock-to-Output Delay
— 250MHz Maximum Clock Frequency
— TTL/3.3V/2.5V Compatible Input Thresholds and
Output Levels (Individually Programmable)
— Low-Power: 16.5mA Quiescent Icc
— 24mA IOL Drive with Programmable Slew Rate
Control Option
— PCI Compatible Drive Capability
— Schmitt Trigger Inputs for Noise Immunity
— Electrically Erasable and Reprogrammable
— Non-Volatile E2CMOS Technology
— 3.3V In-System Programmable Using Boundary Scan
Test Access Port (TAP)
— Change Interconnects in Seconds
— Combinatorial/Latched/Registered Inputs or Outputs
— Individual I/O Tri-state Control with Polarity Control
— Dedicated Clock/Clock Enable Input Pins (two) or
Programmable Clocks/Clock Enables from I/O Pins (20)
— Single Level 4:1 Dynamic Path Selection (Tpd = 3.5ns)
— Programmable Wide-MUX Cascade Feature
Supports up to 16:1 MUX
— Programmable Pull-ups, Bus Hold Latch and Open
Drain on I/O Pins
— Outputs Tri-state During Power-up (“Live Insertion”
— MS Windows or NT / PC-Based or Sun O/S
— Easy Text-Based Design Entry
— Automatic Signal Routing
— Program up to 100 ISP Devices Concurrently
— Simulator Netlist Generation for Easy Board-Level
I/O Pins D
Global Routing
I/O Pins B
The ispGDXVA architecture provides a family of fast,
flexible programmable devices to address a variety of
system-level digital signal routing and interface require-
ments including:
• Multi-Port Multiprocessor Interfaces
• Wide Data and Address Bus Multiplexing
(e.g. 16:1 High-Speed Bus MUX)
• Programmable Control Signal Routing
(e.g. Interrupts, DMAREQs, etc.)
• Board-Level PCB Signal Routing for Prototyping or
Programmable Bus Interfaces
The devices feature fast operation, with input-to-output
signal delays (Tpd) of 3.5ns and clock-to-output delays of
The architecture of the devices consists of a series of
programmable I/O cells interconnected by a Global Rout-
ing Pool (GRP). All I/O pin inputs enter the GRP directly
or are registered or latched so they can be routed to the
required I/O outputs. I/O pin inputs are defined as four
sets (A,B,C,D) which have access to the four MUX inputs
Copyright © 2000 Lattice Semiconductor Corporation. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein
are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8037;
September 2000

80VA Datasheet
Specifications ispGDX80VA
Description (Continued)
found in each I/O cell. Each output has individual, pro-
grammable I/O tri-state control (OE), output latch clock
(CLK), clock enable (CLKEN), and two multiplexer con-
trol (MUX0 and MUX1) inputs. Polarity for these signals
is programmable for each I/O cell. The MUX0 and MUX1
inputs control a fast 4:1 MUX, allowing dynamic selection
of up to four signal sources for a given output. A wider
16:1 MUX can be implemented with the MUX expander
feature of each I/O and a propagation delay increase of
2.0ns. OE, CLK, CLKEN, and MUX0 and MUX1 inputs
can be driven directly from selected sets of I/O pins.
Optional dedicated clock input pins give minimum clock-
to-output delays. CLK and CLKEN share the same set of
I/O pins. CLKEN disables the register clock when
CLKEN = 0.
In addition, there are no pin-to-pin routing constraints for
1:1 or 1:n signal routing. That is, any I/O pin configured
as an input can drive one or more I/O pins configured as
The device pins also have the ability to set outputs to
fixed HIGH or LOW logic levels (Jumper or DIP Switch
mode). Device outputs are specified for 24mA sink and
12mA source current (at JEDEC LVTTL levels) and can
be tied together in parallel for greater drive. On the
ispGDXVA, each I/O pin is individually programmable for
3.3V or 2.5V output levels as described later. Program-
mable output slew rate control can be defined
independently for each I/O pin to reduce overall ground
bounce and switching noise.
Through in-system programming, connections between
I/O pins and architectural features (latched or registered
inputs or outputs, output enable control, etc.) can be
defined. In keeping with its data path application focus,
the ispGDXVA devices contain no programmable logic
arrays. All input pins include Schmitt trigger buffers for
noise immunity. These connections are programmed
into the device using non-volatile E2CMOS technology.
Non-volatile technology means the device configuration
is saved even when the power is removed from the
All I/O pins are equipped with IEEE1149.1-compliant
Boundary Scan Test circuitry for enhanced testability. In
addition, in-system programming is supported through
the Test Access Port via a special set of private com-
The ispGDXVA I/Os are designed to withstand live
insertionsystem environments. The I/O buffers are
disabled during power-up and power-down cycles. When
designing for live insertion,absolute maximum rating
conditions for the Vcc and I/O pins must still be met.
Table 1. ispGDXVA Family Members
ispGDXV/VA Device
ispGDX80VA ispGDX160V/VA ispGDX240VA
I/O Pins
80 160 240
I/O-OE Inputs*
20 40 60
I/O-CLK / CLKEN Inputs*
40 60
I/O-MUXsel1 Inputs*
I/O-MUXsel2 Inputs*
20 40 60
20 40 60
Dedicated Clock Pins**
1 11
BSCAN Interface
1 11
4 44
1 11
Pin Count/Package
100-Pin TQFP
208-Pin PQFP 388-Ball fpBGA
208-Ball fpBGA
272-Ball BGA
* The CLK/CLK_EN, OE, MUX0 and MUX1 terminals on each I/O cell can each be assigned to
25% of the I/Os.
** Global clock pins Y0, Y1, Y2 and Y3 are multiplexed with CLKEN0, CLKEN1, CLKEN2 and
CLKEN3 respectively in all devices.

Features Datasheet pdf ispGDX 80VA TM In-System Programmable 3 .3V Generic Digital Crosspoint TM Feat ures • IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL CROSSPOINT FAMILY — Advanced Architecture Addresses Programmable PC B Interconnect, Bus Interface Integrati on and Jumper/Switch Replacement — Any Input to Any Output” Routing — Fixed HIGH or LOW Output Option for Ju mper/DIP Switch Emulation — Space-Sav ing PQFP and BGA Packaging — Dedicate d IEEE 1149.1-Compliant Boundary Scan T est • HIGH PERFORMANCE E2CMOS® TECHN OLOGY — 3.3V Core Power Supply — 3. 5ns Input-to-Output/3.5ns Clock-to-Outp ut Delay — 250MHz Maximum Clock Frequ ency — TTL/3.3V/2.5V Compatible Input Thresholds and Output Levels (Individu ally Programmable) — Low-Power: 16.5m A Quiescent Icc — 24mA IOL Drive with Programmable Slew Rate Control Option — PCI Compatible Drive Capability — Schmitt Trigger Inputs for Noise Immun ity — Electrically Erasable and Repro grammable — Non-Volatile E2CMOS Technology • ispGDXV™ OFFERS THE FOLLOWING ADVANTAGES — 3.3V In-Syst.
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