Document
July 2000
ML4426* Bi-directional Sensorless BLDC Motor Controller
GENERAL DESCRIPTION
The ML4426 PWM motor controller provides all of the functions necessary for starting and controlling the speed of delta or wye wound Brushless DC (BLDC) motors without Hall Effect sensors. Back EMF voltage is sensed from the motor windings to determine the proper commutation phase sequence using a PLL. This patented sensing technique will commutate a wide range of 3Phase BLDC motors and is insensitive to PWM noise and motor snubbing circuitry. The ML4426 limits the motor current using a constant offtime PWM control loop. The velocity loop is controlled with an onboard amplifier. The ML4426 has circuitry to ensure that there is no shoot-through in directly driven external power MOSFETs. The timing of the start-up sequence is determined by the selection of three timing capacitors. This allows optimization for a wide range of motors and loads.
FEATURES
s Motor starts and stops with power to IC
s Bi-directional motor drive for applications requiring forward/ reverse operation s On-board start sequence: Align ® Ramp ® Set Speed s Patented Back-EMF commutation technique provides jitterless torque for minimum “spin-up” time s Onboard speed control loop s PLL used for commutation provides noise immunity from PWM spikes, compared to noise sensitive zero crossing technique s PWM control for maximum efficiency s Direct FET drive for 12V motors; drives high voltage motors with IC buffers from IR, IXYS, Harris, Power Integrations, Siliconix, etc. (* Indicates Part Is End Of Life As Of July 1, 2000)
BLOCK DIAGRAM (Pin Configuration Shown for 28 Pin Version)
17 VDD 750nA FB A 22 FB B 23 FB C 24 BACK EMF SAMPLER 1.5V
– +
CAT 750nA
VDD
19 CRT
–
21 CRR
20 SPEED CVCO FB
15
16 RVCO
1.5V
+
VDD 500nA VOLTAGE CONTROLLED OSCILLATOR VCO/TACH 13
VCO OUT
F/R 12
+
VCO OUT
R A F B
COMMUTATION STATE MACHINE HA HB GATING LOGIC & OUTPUT DRIVERS UVLO HC LA LB LC UV FAULT REFERENCE 2 3 4 9 10 11 18
8 SPEED SET 5 SPEED COMP
–
3.9V
– +
E D
C
1.7V 6 CT 20kHz 1 ISENSE 1.7V ×5 VREF 16kΩ
– +
–
ILIMIT 1-SHOT
1.4V VDD 4kΩ
+
8kΩ 26 CIOS BRAKE 25 14 VDD
GND 28 27
RREF
7
VREF
1
ML4426
PIN CONFIGURATION
ML4426 28-Pin Narrow PDIP (P28N) 28-Pin SOIC (S28)
ISENSE HA HB HC SPEED COMP CT VREF SPEED SET LA 1 2 3 4 5 6 7 8 9 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GND RREF CIOS BRAKE FB C FB B FB A CRR SPEED FB CRT UV FAULT CAT RVCO CVCO
LB 10 LC 11 F/R 12 VCO/TACH 13 VDD 14
TOP VIEW
ML4425 32-Pin TQFP (H32-7)
ISENSE BRAKE GND CIOS RREF HA NC HB
H3 NC SPEED COMP CT VREF SPEED SET LA LB
32 31 30 29 28 27 26 25 24 1 2 3 4 5 6 7 8 9 23 22 21 20 19 18 17 10 11 12 13 14 15 16
FB C FB B FB A CRR SPEED FB CRT UV FAULT CAT
LC
F/R
VCO/TACH
VDD
NC
NC
CVCO
TOP VIEW
2
RVCO
ML4426
PIN DESCRIPTION
PIN NAME
(Pin number in parenthesis is for TQFP package)
PIN NAME FUNCTION
FUNCTION
1(30)
I SENSE
Motor current sense input. When ISENSE exceeds 0.2 ´ ILIMIT, the output drivers LA, LB, and LC are shut off for a fixed time determined by CIOS Active low output driver for the phase A high-side switch Active low output driver for the phase B high-side switch Active low output driver for the phase C high-side switch
17(17) CAT
A capacitor to GND sets the time that the controller stays in the align mode This output goes low when VDD drops below the UVLO threshold, and indicates that all output drivers have been disabled A capacitor to GND sets the time that the controller stays in the ramp mode Output of the back-EMF sampling circuit and input to the VCO. An RC network connected to SPEED FB sets the compensation for the PLL loop formed by the back-EMF sampling circuit, the VCO, and the commutation state machine A capacitor to between CRR and SPEED FB sets the ramp rate (acceleration) of the motor when the controller is in ramp mode The motor feedback voltage from phase A is monitored through a resistor divider for back-EMF sensing at this pin The motor feedback voltage from phase B is monitored through a resistor divider for back-EMF sensing at this pin The motor feedback voltage from phase C is monitored through a resistor divider for back-EMF sensing at this pin A logic low input activates motor braking by shutting off the highside output drivers and turning on the low-side output drivers A capacitor to GND sets the time that the low-side output drivers remain off after ISENSE exceeds its threshold An 137kW resistor to GND sets a current proportional to VREF that is used to set all the internal bias currents except for the VCO Signal and power ground
18(18) UV FAULT
2(31) 3(32) 4(1) 5(3)
HA HB HC
19(19) CRT
20(20) SPEED FB
SPEED COMP Speed control loop compensation is set by a series resistor and capacitor from SPEED COMP to GND CT V REF SPEED SET A capacitor from CT to GND sets the PWM oscillator frequency 6.9V reference voltage output Speed loop input which ranges from 0 (stopped) to VREF (maximum speed) Active high output driver .