CMOS RAM. 81C55 Datasheet

81C55 Datasheet PDF, Equivalent


Part Number

81C55

Description

Radiation Hardened 256 x 8 CMOS RAM

Manufacture

Intersil Corporation

Total Page 14 Pages
PDF Download
Download 81C55 Datasheet PDF


81C55 Datasheet
March 1996
HS-81C55RH,
HS-81C56RH
Radiation Hardened
256 x 8 CMOS RAM
Features
• Devices QML Qualified in Accordance with
MIL-PRF-38535
• Detailed Electrical and Screening Requirements are
Contained in SMD# 5962-95818 and Intersil’ QM Plan
• Radiation Hardened EPI-CMOS
- Parametrics Guaranteed 1 x 105 RAD(Si)
- Transient Upset > 1 x 108 RAD(Si)/s
- Latch-Up Free > 1 x 1012 RAD(Si)/s
• Electrically Equivalent to Sandia SA 3001
• Pin Compatible with Intel 8155/56
• Bus Compatible with HS-80C85RH
• Single 5V Power Supply
• Low Standby Current 200µA Max
• Low Operating Current 2mA/MHz
• Completely Static Design
• Internal Address Latches
• Two Programmable 8-Bit I/O Ports
• One Programmable 6-Bit I/O Port
• Programmable 14-Bit Binary Counter/Timer
• Multiplexed Address and Data Bus
• Self Aligned Junction Isolated (SAJI) Process
• Military Temperature Range -55oC to +125oC
Description
The HS-81C55/56RH are radiation hardened RAM and I/O
chips fabricated using the Intersil radiation hardened Self-
Aligned Junction Isolated (SAJI) silicon gate technology.
Latch-up free operation is achieved by the use of epitaxial
starting material to eliminate the parasitic SCR effect seen in
conventional bulk CMOS devices.
The HS-81C55/56RH is intended for use with the
HS-80C85RH radiation hardened microprocessor system. The
RAM portion is designed as 2048 static cells organized as 256
x 8. A maximum post irradiation access time of 500ns allows
the HS-81C55/56RH to be used with the HS-80C85RH CPU
without any wait states. The HS-81C55RH requires an active
low chip enable while the HS-81C56RH requires an active high
chip enable. These chips are designed for operation utilizing a
single 5V power supply.
Functional Diagram
IO/M
AD0 - AD7
CE OR CE
ALE
RD
WR
RESET
TIMER CLK
TIMER OUT
256 x 8
STATIC
RAM
PORT A
A 8 PA0 - PA7
PORT B
B 8 PB0 - PB7
TIMER
PORT C
C 8 PC0 - PC5
VDD (10V)
GND
81C55RH = CE
81C56RH = CE
Ordering Information
PART NUMBER
5962R9XXXX01QRC
5962R9XXXX01VRC
5962R9XXXX01QXC
5962R9XXXX01VXC
5962R9XXXX02QRC
5962R9XXXX02VRC
5962R9XXXX02QXC
5962R9XXXX02VXC
HS1-81C55RH/Sample
HS9-81C55RH/Sample
HS1-81C56RH/Sample
HS9-81C56RH/Sample
TEMPERATURE RANGE
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
+25oC
+25oC
+25oC
+25oC
SCREENING LEVEL
MIL-PRF-38535 Level Q
MIL-PRF-38535 Level V
MIL-PRF-38535 Level Q
MIL-PRF-38535 Level V
MIL-PRF-38535 Level Q
MIL-PRF-38535 Level V
MIL-PRF-38535 Level Q
MIL-PRF-38535 Level V
Sample
Sample
Sample
Sample
PACKAGE
40 Lead SBDIP
40 Lead SBDIP
42 Lead Ceramic Flatpack
42 Lead Ceramic Flatpack
40 Lead SBDIP
40 Lead SBDIP
42 Lead Ceramic Flatpack
42 Lead Ceramic Flatpack
40 Lead SBDIP
42 Lead Ceramic Flatpack
40 Lead SBDIP
42 Lead Ceramic Flatpack
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
Spec Number 518056
File Number 3039.1

81C55 Datasheet
Pinouts
HS-81C55RH, HS-81C56RH
40 LEAD DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T40
TOP VIEW
PC3 1
PC4 2
TIMER IN 3
RESET 4
PC5 5
TIMER OUT 6
IO / M 7
CE or CE* 8
RD 9
*81C55RH = CE
81C56RH = CE
WR 10
ALE 11
AD0 12
AD1 13
AD2 14
AD3 15
AD4 16
AD5 17
AD6 18
AD7 19
GND 20
40 VDD
39 PC2
38 PC1
37 PC0
36 PB7
35 PB6
34 PB5
33 PB4
32 PB3
31 PB2
30 PB1
29 PB0
28 PA7
27 PA6
26 PA5
25 PA4
24 PA3
23 PA2
22 PA1
21 PA0
42 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
INTERSIL OUTLINE K42.A
TOP VIEW
PC3
PC4
TIMER IN
RESET
PC5
TIMER OUT
IO/M
CE OR CE
RD
WR
ALE
AD0
AD1
AD2
AD3
NC
AD4
AD5
AD6
AD7
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42 VDD
41 PC2
40 PC1
39 PC0
38 PB7
37 PB6
36 PB5
35 PB4
34 PB3
33 PB2
32 PB1
31 PB0
30 PA7
29 PA6
28 PA5
27 NC
26 PA4
25 PA3
24 PA2
23 PA1
22 PA0
Spec Number 518056
2


Features Datasheet pdf HS-81C55RH, HS-81C56RH March 1996 Radia tion Hardened 256 x 8 CMOS RAM Descript ion The HS-81C55/56RH are radiation har dened RAM and I/O chips fabricated usin g the Intersil radiation hardened SelfA ligned Junction Isolated (SAJI) silicon gate technology. Latch-up free operati on is achieved by the use of epitaxial starting material to eliminate the para sitic SCR effect seen in conventional b ulk CMOS devices. The HS-81C55/56RH is intended for use with the HS-80C85RH ra diation hardened microprocessor system. The RAM portion is designed as 2048 st atic cells organized as 256 x 8. A maxi mum post irradiation access time of 500 ns allows the HS-81C55/56RH to be used with the HS-80C85RH CPU without any wai t states. The HS-81C55RH requires an ac tive low chip enable while the HS-81C56 RH requires an active high chip enable. These chips are designed for operation utilizing a single 5V power supply. F eatures • Devices QML Qualified in A ccordance with MIL-PRF-38535 • Detailed Electrical and Screening Re.
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