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81C56 Dataheets PDF



Part Number 81C56
Manufacturers Intersil Corporation
Logo Intersil Corporation
Description Radiation Hardened 256 x 8 CMOS RAM
Datasheet 81C56 Datasheet81C56 Datasheet (PDF)

HS-81C55RH, HS-81C56RH March 1996 Radiation Hardened 256 x 8 CMOS RAM Description The HS-81C55/56RH are radiation hardened RAM and I/O chips fabricated using the Intersil radiation hardened SelfAligned Junction Isolated (SAJI) silicon gate technology. Latch-up free operation is achieved by the use of epitaxial starting material to eliminate the parasitic SCR effect seen in conventional bulk CMOS devices. The HS-81C55/56RH is intended for use with the HS-80C85RH radiation hardened microprocessor.

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HS-81C55RH, HS-81C56RH March 1996 Radiation Hardened 256 x 8 CMOS RAM Description The HS-81C55/56RH are radiation hardened RAM and I/O chips fabricated using the Intersil radiation hardened SelfAligned Junction Isolated (SAJI) silicon gate technology. Latch-up free operation is achieved by the use of epitaxial starting material to eliminate the parasitic SCR effect seen in conventional bulk CMOS devices. The HS-81C55/56RH is intended for use with the HS-80C85RH radiation hardened microprocessor system. The RAM portion is designed as 2048 static cells organized as 256 x 8. A maximum post irradiation access time of 500ns allows the HS-81C55/56RH to be used with the HS-80C85RH CPU without any wait states. The HS-81C55RH requires an active low chip enable while the HS-81C56RH requires an active high chip enable. These chips are designed for operation utilizing a single 5V power supply. Features • Devices QML Qualified in Accordance with MIL-PRF-38535 • Detailed Electrical and Screening Requirements are Contained in SMD# 5962-95818 and Intersil’ QM Plan • Radiation Hardened EPI-CMOS - Parametrics Guaranteed 1 x 105 RAD(Si) - Transient Upset > 1 x 108 RAD(Si)/s - Latch-Up Free > 1 x 1012 RAD(Si)/s • Electrically Equivalent to Sandia SA 3001 • Pin Compatible with Intel 8155/56 • Bus Compatible with HS-80C85RH • Single 5V Power Supply • Low Standby Current 200µA Max • Low Operating Current 2mA/MHz • Completely Static Design • Internal Address Latches • Two Programmable 8-Bit I/O Ports • One Programmable 6-Bit I/O Port • Programmable 14-Bit Binary Counter/Timer • Multiplexed Address and Data Bus • Self Aligned Junction Isolated (SAJI) Process • Military Temperature Range -55oC to +125oC Functional Diagram IO/M AD0 - AD7 CE OR CE † ALE RD WR RESET TIMER CLK TIMER OUT † 81C55RH = CE 81C56RH = CE TIMER C PORT C 8 PC0 - PC5 VDD (10V) GND 256 x 8 STATIC RAM A PORT A 8 PA0 - PA7 PORT B B 8 PB0 - PB7 Ordering Information PART NUMBER 5962R9XXXX01QRC 5962R9XXXX01VRC 5962R9XXXX01QXC 5962R9XXXX01VXC 5962R9XXXX02QRC 5962R9XXXX02VRC 5962R9XXXX02QXC 5962R9XXXX02VXC HS1-81C55RH/Sample HS9-81C55RH/Sample HS1-81C56RH/Sample HS9-81C56RH/Sample TEMPERATURE RANGE -55oC to +125oC SCREENING LEVEL MIL-PRF-38535 Level Q MIL-PRF-38535 Level V MIL-PRF-38535 Level Q MIL-PRF-38535 Level V MIL-PRF-38535 Level Q MIL-PRF-38535 Level V MIL-PRF-38535 Level Q MIL-PRF-38535 Level V Sample Sample Sample Sample PACKAGE 40 Lead SBDIP 40 Lead SBDIP 42 Lead Ceramic Flatpack 42 Lead Ceramic Flatpack 40 Lead SBDIP 40 Lead SBDIP 42 Lead Ceramic Flatpack 42 Lead Ceramic Flatpack 40 Lead SBDIP 42 Lead Ceramic Flatpack 40 Lead SBDIP 42 Lead Ceramic Flatpack -55oC to +125oC -55oC -55oC -55oC to to to +125oC +125oC +125oC -55oC to +125oC -55oC -55oC to to +125oC +125oC +25oC +25oC +25oC +25oC CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 Spec Number File Numbe.


81C55 81C56 81CNQ


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