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ML6553 Dataheets PDF



Part Number ML6553
Manufacturers Fairchild
Logo Fairchild
Description Bus Termination Regulator
Datasheet ML6553 DatasheetML6553 Datasheet (PDF)

www.fairchildsemi.com ML6553 Bus Termination Regulator Features • Can source and sink up to 1A • Generates termination voltages for DDR SDRAM, SSTL_2 SDRAM, SGRAM, or equivalent memories • Generates termination voltages for active termination schemes for GTL+, DDR, Rambus™, VME, LV-TTL, PECL and other high speed logic • VL regulated to within 3% at 800mA • Minimum external components. Requires no feedback compensation • Fixed frequency operation for easier system integration • Lower power cons.

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www.fairchildsemi.com ML6553 Bus Termination Regulator Features • Can source and sink up to 1A • Generates termination voltages for DDR SDRAM, SSTL_2 SDRAM, SGRAM, or equivalent memories • Generates termination voltages for active termination schemes for GTL+, DDR, Rambus™, VME, LV-TTL, PECL and other high speed logic • VL regulated to within 3% at 800mA • Minimum external components. Requires no feedback compensation • Fixed frequency operation for easier system integration • Lower power consumption than passive, resistor divider termination, reducing heat by as much as 50% • Separate voltages for VCCQ and PVDD General Description The ML6553 switching regulator is designed to convert voltage supplies ranging from 2.0V to 3.6V into a desired output voltage or termination voltage for various applications. The ML6553 can be implemented to produce regulated output voltages in two different modes. In the default mode, the output is 50% of voltage applied to VCCQ. The switching regulator is capable of sourcing or sinking up to 1A of current. The ML6553, used in conjunction with series termination resistors, provides an excellent voltage source for active termination schemes of high speed transmission lines as those seen in high speed memory buses and distributed backplane designs. The voltage output of the regulator can be used as a termination voltage for other bus interface standards such as SSTL, DDR, Rambus™, GTL+, VME, LV-CMOS, LV-TTL, P-ECL, and CMOS. Block Diagram 1 VCCQ 4 AVCC CLK OSCILLATOR/ RAMP GENERATOR BUFFER RAMP S – R + + 190kΩ – VINTEG + PWM COMPARATOR Q Q 5 PVDD VL Q1 VL 7 Q2 DGND 8 6 190kΩ VCCQ/2 2 – AGND 3 REV. 1.0.2 3/21/01 ML6553 PRODUCT SPECIFICATION Pin Configuration ML6553 8-Pin SOIC (S08) VCCQ VCCQ/2 AGND AVCC 1 2 3 4 8 7 6 5 DGND VL VL PVDD TOP VIEW Pin Description Pin 1 2 3 4 5 6 7 8 Name VCCQ VCCQ/2 AGND AVCC PVDD VL VL DGND VREF output is VCCQ/2 Analog signal ground Voltage supply for the noise sensitive analog control section. Voltage supply for the internal power transistors. Output inductor connection Output inductor connection Return for the internal power transistors. Function Voltage supply for internal reference voltage divider Absolute Maximum Ratings Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Parameter VIN Voltage on Any Other Pin Peak Switch Current (IPEAK) Average Switch Current (IAVG) Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10 sec) Thermal Resistance (θJA) Output Current, Source or Sink –65 GND – 0.3 Min. Max. 5 VIN + 0.3 1 300 150 150 150 160 1 Unit V V A mA °C °C °C °C/W A Operating Conditions Temperature Range AVCC, PVDD Operating Range 0°C to 70°C 2.0V to 3.6V 2 REV. 1.0.2 3/21/01 PRODUCT SPECIFICATION ML6553 Electrical Characteristics AVCC = PVDD = 3.3V ±10%. Unless otherwise specified, TA = Operating .


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