DatasheetsPDF.com

82375EB Dataheets PDF



Part Number 82375EB
Manufacturers Intel Corporation
Logo Intel Corporation
Description PCI-EISA BRIDGE
Datasheet 82375EB Datasheet82375EB Datasheet (PDF)

82375EB 82375SB PCI-EISA BRIDGE (PCEB) Y Provides the Bridge Between the PCI Local Bus and EISA Bus 100% PCI and EISA Compatible PCI and EISA Master Slave Interface Directly Drives 10 PCI Loads and 8 EISA Slots Supports PCI from 25 to 33 MHz Data Buffers Improve Performance Four 32-bit PCI-to-EISA Posted Write Buffers Four 16-byte EISA-to-PCI Read Write Line Buffers EISA-to-PCI Read Prefetch EISA-to-PCI and PCI-to-EISA Write Posting Data Buffer Management Ensures Data Coherency Flush Posted Wri.

  82375EB   82375EB


Document
82375EB 82375SB PCI-EISA BRIDGE (PCEB) Y Provides the Bridge Between the PCI Local Bus and EISA Bus 100% PCI and EISA Compatible PCI and EISA Master Slave Interface Directly Drives 10 PCI Loads and 8 EISA Slots Supports PCI from 25 to 33 MHz Data Buffers Improve Performance Four 32-bit PCI-to-EISA Posted Write Buffers Four 16-byte EISA-to-PCI Read Write Line Buffers EISA-to-PCI Read Prefetch EISA-to-PCI and PCI-to-EISA Write Posting Data Buffer Management Ensures Data Coherency Flush Posted Write Buffers Flush or Invalidate Line Buffers System-Wide Data Buffer Coherency Control Burst Transfers on both the PCI and EISA Buses 32-Bit Data Paths Y Y Integrated EISA Data Swap Buffers Arbitration for PCI Devices Supports Six PCI Masters Fixed Rotating or a Combination of the Two Supports External PCI Arbiter and Arbiter Cascading PCI and EISA Address Decoding and Mapping Positive Decode of Main Memory Areas (MEMCS Generation) Four Programmable PCI Memory Space Regions Four Programmable PCI I O Space Regions Programmable Main Memory Address Decoding Main Memory Sizes up to 512 MBytes Access Attributes for 15 Memory Segments in First 1 MByte of Main Memory Programmable Main Memory Hole Integrated 16-bit BIOS Timer Only Available as Part of a Supported Kit Y Y Y Y Y Y Y Y Y The 82375EB SB PCI-EISA Bridge (PCEB) provides the master slave functions on both the PCI Local Bus and the EISA Bus Functioning as a bridge between the PCI and EISA buses the PCEB provides the address and data paths bus controls and bus protocol translation for PCI-to-EISA and EISA-to-PCI transfers Extensive data buffering in both directions increases system performance by maximizing PCI and EISA Bus efficiency and allowing concurrency on the two buses The PCEB’s buffer management mechanism ensures data coherency The PCEB integrates central bus control functions including a programmable bus arbiter for the PCI Bus and EISA data swap buffers for the EISA Bus Integrated system functions include PCI parity generation system error reporting and programmable PCI and EISA memory and I O address space mapping and decoding The PCEB also contains a BIOS Timer that can be used to implement timing loops The PCEB is intended to be used with the EISA System Component (ESC) to provide an EISA I O subsystem interface This document describes both the 82375EB and 82375SB components Unshaded areas describe the 82375EB Shaded areas like this one describe the 82375SB operations that differ from the 82375EB Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata COPYRIGHT INTEL CORPORATION 1996 March 1996 Order Number 290477-004 82375EB SB 290477 – 1 PCEB Simplified Block Diagram 2 82375EB 82375SB PCI-EISA BRIDGE (PCEB) CONTENTS 1 0 ARCHITECTURAL OVERVIEW 1 1 PCEB Overview 1 2 ESC Overview 2 0 SIGNAL DESCRIPTION 2 1 PCI Bus Interface Signals 2 2 PCI Arbiter Signals 2 3 Address Decoder Signals 2 4 EISA Interface Signals 2 5 ISA Interface Signals 2 6 PCEB ESC Interface Signals 2 7 Test Signal 3 0 REGISTER DESCRIPTION 3 1 Configuration Registers 3 1 1 VID VENDOR IDENTIFICATION REGISTER 3 1 2 DID DEVICE IDENTIFICATION REGISTER 3 1 3 PCICMD PCI COMMAND REGISTER 3 1 4 PCISTS PCI STATUS REGISTER 3 1 5 RID REVISION IDENTIFICATION REGISTER 3 1 6 MLT MASTER LATENCY TIMER REGISTER 3 1 7 PCICON PCI CONTROL REGISTER 3 1 8 ARBCON PCI ARBITER CONTROL REGISTER 3 1 9 ARBPRI PCI ARBITER PRIORITY CONTROL REGISTER 3 1 10 ARBPRIX PCI ARBITER PRIORITY CONTROL EXTENSION REGISTER 3 1 11 MCSCON MEMCS CONTROL REGISTER 3 1 12 MCSBOH MEMCS BOTTOM OF HOLE REGISTER 3 1 13 MCSTOH MEMCS TOP OF HOLE REGISTER 3 1 14 MCSTOM MEMCS TOP OF MEMORY REGISTER 3 1 15 EADC1 EISA ADDRESS DECODE CONTROL 1 REGISTER 3 1 16 IORT ISA I O RECOVERY TIMER REGISTER 3 1 17 MAR1 MEMCS ATTRIBUTE REGISTER 1 3 1 18 MAR2 MEMCS ATTRIBUTE REGISTER 2 3 1 19 MAR3 MEMCS ATTRIBUTE REGISTER 3 3 1 20 PDCON PCI DECODE CONTROL REGISTER 3 1 21 EADC2 EISA ADDRESS DECODE CONTROL EXTENSION REGISTER PAGE 8 10 12 14 15 18 19 20 23 24 26 27 27 29 29 30 31 31 32 32 33 34 35 35 36 37 37 38 39 40 40 41 42 43 3 CONTENTS 3 1 22 EPMRA EISA-TO-PCI MEMORY REGION ATTRIBUTES REGISTER 3 1 23 MEMREGN 4 1 EISA-TO-PCI MEMORY REGION ADDRESS REGISTERS 3 1 24 IOREGN 4 1 EISA-TO-PCI I O REGION ADDRESS REGISTERS 3 1 25 BTMR BIOS TIMER BASE ADDRESS REGISTER 3 1 26 ELTCR EISA LATENCY TIMER CONTROL REGISTER 3 2 I O Registers 3 2 1 BIOSTM BIOS TIMER REGISTER 4 0 ADDRESS DECODING 4 1 PCI Cycle Address Decoding 4 1 1 MEMORY SPACE ADDRESS DECODING 4 1 1 1 Main Memory Decoding (MEMCS ) 4 1.


82374SB 82375EB 82375SB


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)