NETWORK COPROCESSOR. 82596DX Datasheet

82596DX Datasheet PDF, Equivalent


Part Number

82596DX

Description

HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR

Manufacture

Intel Corporation

Total Page 30 Pages
PDF Download
Download 82596DX Datasheet PDF


82596DX Datasheet
82596DX AND 82596SX
HIGH-PERFORMANCE 32-BIT LOCAL
AREA NETWORK COPROCESSOR
Y Performs Complete CSMA CD Medium
Access Control (MAC) Functions
Independently of CPU
IEEE 802 3 (EOC) Frame Delimiting
Y Supports Industry Standard LANs
IEEE TYPE 10BASE-T (TPE)
IEEE TYPE 10BASE5 (Ethernet )
IEEE TYPE 10BASE2 (Cheapernet)
IEEE TYPE 1BASE5 (StarLAN)
and the Proposed Standard
TYPE 10BASE-F
Proprietary CSMA CD Networks Up
to 20 Mb s
Y On-Chip Memory Management
Automatic Buffer Chaining
Buffer Reclamation after Receipt of
Bad Frames Optional Save Bad
Frames
32-Bit Segmented or Linear (Flat)
Memory Addressing Formats
Y 82586 Software Compatible
Y Optimized CPU Interface
82596DX Bus Interface Optimized to
Intel’s 32-Bit i386TMDX
82596SX Bus Interface Optimized to
Intel’s 16-Bit i386TMSX
Supports Big Endian and Little
Endian Byte Ordering
Y High-Performance 16- 32-Bit Bus
Master Interface
66-MB s Bus Bandwidth
33-MHz Clock Two Clocks Per
Transfer
Bus Throttle Timers
Transfers Data at 100% of Serial
Bandwidth
128-Byte Receive FIFO 64-Byte
Transmit FIFO
Y Network Management and Diagnostics
Monitor Mode
32-Bit Statistical Counters
Y Self-Test Diagnostics
Y Configurable Initialization Root for Data
Structures
Y High-Speed 5-V CHMOS IV
Technology
Y 132-Pin Plastic Quad Flat Pack (PQFP)
and PGA Package
(See Packaging Specifications Order Number 240800-001
Package Type KU and A)
i386TM is a trademark of Intel Corporation
Ethernet is a registered trademark of Xerox Corporation
CHMOS is a patented process of Intel Corporation
Figure 1 82596DX SX Block Diagram
290219 – 1
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1996
November 1995
Order Number 290219-006

82596DX Datasheet
82596DX SX
82596DX and 82596SX High-Performance
32-Bit Local Area Network Coprocessor
CONTENTS
PAGE
INTRODUCTION
3
PIN DESCRIPTIONS
10
82596 AND HOST CPU
INTERACTION
14
82596 BUS INTERFACE
14
82596 MEMORY ADDRESSING
14
82596 SYSTEM MEMORY
STRUCTURE
16
TRANSMIT AND RECEIVE MEMORY
STRUCTURES
17
TRANSMITTING FRAMES
20
RECEIVING FRAMES
21
82596 NETWORK MANAGEMENT AND
DIAGNOSTICS
21
NETWORK PLANNING AND
MAINTENANCE
23
STATION DIAGNOSTICS AND SELF-
TEST
24
82586 SOFTWARE COMPATIBILITY
24
INITIALIZING THE 82596
24
SYSTEM CONFIGURATION POINTER
(SCP)
Writing the Sysbus
24
25
INTERMEDIATE SYSTEM
CONFIGURATION POINTER
(ISCP)
26
INITIALIZATION PROCESS
26
CONTROLLING THE 82596DX SX
27
82596 CPU ACCESS INTERFACE
(PORT )
27
MEMORY ADDRESSING FORMATS
28
LITTLE ENDIAN AND BIG ENDIAN
BYTE ORDERING
28
COMMAND UNIT (CU)
29
RECEIVE UNIT (RU)
30
SYSTEM CONTROL BLOCK (SCB)
30
SCB OFFSET ADDRESSES
33
CONTENTS
CBL Offset (Address)
RFA Offset (Address)
SCB STATISTICAL COUNTERS
Statistical Counter Operation
ACTION COMMANDS AND
OPERATING MODES
NOP
Individual Address Setup
Configure
Multicast-Setup
Transmit
Jamming Rules
TDR
Dump
Diagnose
RECEIVE FRAME DESCRIPTOR
Simplified Memory Structure
Flexible Memory Structure
Receive Buffer Descriptor (RBD)
PGA PACKAGE THERMAL
SPECIFICATION
ELECTRICAL AND TIMING
CHARACTERISTICS
Absolute Maximum Ratings
DC Characteristics
AC Characteristics
82596DX Input Output System
Timings
82596SX Input Output System
Timings
Transmit Receive Clock
Parameters
82596DX SX BUS OPERATION
System Interface A C Timing
Characteristics
Input Waveforms
Serial A C Timing Characteristics
OUTLINE DIAGRAMS
REVISION SUMMARY
2
PAGE
33
34
34
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35
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43
44
46
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Features Datasheet pdf 82596DX AND 82596SX HIGH-PERFORMANCE 32- BIT LOCAL AREA NETWORK COPROCESSOR Y P erforms Complete CSMA CD Medium Access Control (MAC) Functions Independently o f CPU IEEE 802 3 (EOC) Frame Delimiting Supports Industry Standard LANs IEEE T YPE 10BASE-T (TPE) IEEE TYPE 10BASE5 (E thernet ) IEEE TYPE 10BASE2 (Cheapernet ) IEEE TYPE 1BASE5 (StarLAN) and the Pr oposed Standard TYPE 10BASE-F Proprieta ry CSMA CD Networks Up to 20 Mb s On-Ch ip Memory Management Automatic Buffer C haining Buffer Reclamation after Receip t of Bad Frames Optional Save Bad Frame s 32-Bit Segmented or Linear (Flat) Mem ory Addressing Formats 82586 Software C ompatible Optimized CPU Interface 82596 DX Bus Interface Optimized to Intel’s 32-Bit i386 TM DX 82596SX Bus Interfac e Optimized to Intel’s 16-Bit i386 TM SX Supports Big Endian and Little Endi an Byte Ordering Y Y High-Performanc e 16- 32-Bit Bus Master Interface 66-MB s Bus Bandwidth 33-MHz Clock Two Clock s Per Transfer Bus Throttle Timers Transfers Data at 100% of Serial.
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