Document
MM74C164 8-Bit Parallel-Out Serial Shift Register
October 1987 Revised January 1999
MM74C164 8-Bit Parallel-Out Serial Shift Register
General Description
The MM74C164 shift registers are a monolithic complementary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement transistors. These 8-bit shift registers have gated serial inputs and clear. Each register bit is a D-type master/slave flip-flop. A high-level input enables the other input which will then determine the state of the flip-flop. Data is serially shifted in and out of the 8-bit register during the positive going transition of clock pulse. Clear is independent of the clock and accomplished by a low level at the clear input. All inputs are protected against electrostatic effects.
Features
s Supply voltage range: s High noise immunity: 3V to 15V drive 2 LPTTL loads 0.45 VCC (typ.) s Tenth power TTL compatible: s Low power: 50 nW (typ.) s Medium speed operation: 0.8 MHz (typ.) with 10V supply
Applications
• Data terminals • Instrumentation • Medical electronics • Alarm systems • Industrial electronics • Remote metering • Computers
Ordering Code:
Order Number MM74C164M MM74C164N Package Number M14A N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow 14-Lead Plastic Dual-In-Line (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP and SOIC
Truth Table
Serial Inputs A and B Inputs tn A 1 0 1 0 B 1 1 0 0 Output tn+1 QA 1 0 0 0
Top View
© 1999 Fairchild Semiconductor Corporation
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MM74C164
Block Diagram
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MM74C164
Absolute Maximum Ratings(Note 1)
Voltage at Any Pin Operating Temperature Range Storage Temperature Range Absolute Maximum VCC Power Dissipation (PD) Dual-In-Line Small Outline 700 mW 500 mW −0.3V to VCC + 0.3V −40°C to +85°C −65°C to +150°C 18V
Operating VCC Range Lead Temperature (soldering, 10 seconds)
3V to 15V 260°C
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation.
DC Electrical Characteristics
Min/Max limits apply across temperature range unless otherwise noted Symbol CMOS TO CMOS VIN(1) VIN(0) VOUT(1) VOUT(0) IIN(1) IIN(0) ICC VIN(1) VIN(0) VOUT(1) VOUT(0) ISOURCE ISOURCE ISINK ISINK Logical “1” Input Voltage Logical “0” Input Voltage Logical “1” Output Voltage Logical “0” Output Voltage Logical “1” Input Current Logical “0” Input Current Supply Current Logical “1” Input Voltage Logical “0” Input Voltage Logical “1” Output Voltage Logical “0” Output Voltage Output Source Current Output Source Current Output Sink Current Output Sink Current VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V, IO = −10 µA VCC = 10V, IO = −10 µA VCC = 5V, IO = +10 µA VCC = 10V, IO = +10 µA VCC = 15V, VIN = 15V VCC = 15V, VIN = 0V VCC = 15V VCC = 4.75V VCC = 4.75V VCC = 4.75V, IO = −360 µA VCC = 4.75V, IO = 360 µA VCC = 5V, VIN(0) = 0V TA = 25°C, VOUT = 0V VCC = 10V, VIN(0) = 0V TA = 25°C, VOUT = 0V VCC = 5V, VIN(1) = 5V TA = 25°C, VOUT = VCC VCC = 10V, VIN(1) = 10V TA = 25°C, VOUT = VCC 8.0 mA 1.75 mA −8.0 mA −1.75 2.4 0.4 VCC − 1.5 0.8 −1.0 0.005 −0.005 0.05 300 4.5 9.0 0.5 1.0 1.0 3.5 8.0 1.5 2.0 V V V V V V V V µA µA µA V V V V mA Parameter Conditions Min Typ Max Units
CMOS TO LPTTL INTERFACE
OUTPUT DRIVE (See Family Characteristics Data Sheet) (Short Circuit Current)
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MM74C164
AC Electrical Characteristics
TA = 25°C, CL = 50 pF, unless otherwise noted Symbol tpd1 tpd0 tS tH fMAX tW tr, tf CIN CPD Parameter Propagation Delay Time to a Logical “0” or a Logical “1” from Clock to Q Clear to Q Time Prior to Clock Pulse that Data Must be Present Time After Clock Pulse that Data Must be Held Maximum Clock Frequency Minimum Clear Pulse Width Maximum Clock Rise and Fall Time Input Capacitance Power Dissipation Capacitance
(Note 2)
Conditions VCC = 5V VCC = 10V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V Any Input (Note 3) (Note 4) 15 5 5 140 200 80 0 0 2.0 5.5 Min Typ 230 90 280 110 110 30 0 0 3 8 150 55 250 90 Max 310 120 380 150 Units ns ns ns ns ns ns ns ns MHz MHz ns ns µs µs pF pF
Propagation Delay Time to a Logical “0” from VCC = 5V
Note 2: AC Parameters are guaranteed by DC correlated testing. Note 3: Capacitance is guaranteed by periodic testing. Note 4: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics application note AN-90.
Typical Applications
74C Compatibility
Guaranteed Noise Margin as a Function of VCC
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MM74C164
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