MM74C175

MM74C175 Quad D-Type Flip-Flop October 1987 Revised January 1999 MM74C175 Quad D-Type Flip-Flop General Description The MM74C175 consists of four positive-edge triggered Dtype flip-flops implemented with monolithic CMOS technology. Both are true and complemented outputs from each flip-flop are externally available. All four flip-flops are controlled by a common clock and a common clear. Information at the D-type inputs meeting the set-up time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. The clearing operation, enabled by a negative pulse at Clear input, clears all four Q outputs to logical “0” and Q's to logical “1”. All inputs are protected from static discharge by diode clamps to VCC and GND. Features s Wide supply voltage range: s Guaranteed noise margin: s High noise immunity: 3V to 15V 1.0V 0.45 VCC (typ.) Fan out of 2 driving 74L s Low power TTL compatibility: Ordering Code: Order Number MM74C175M MM74C175N Package Number M16A N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Assignments for DIP and SOIC Truth Table Each Flip-Flop Inputs Clear L H H H H Clock X ↑ ↑ H L D X H L X X Outputs Q L H L NC NC Q H L H NC NC H = HIGH Level L = LOW Level X = Irrelevant ↑ = Transitio...