D-Type Latch. MM74C373 Datasheet


MM74C373 Latch. Datasheet pdf. Equivalent


Part Number

MM74C373

Description

3-STATE Octal D-Type Latch

Manufacture

Fairchild

Total Page 11 Pages
Datasheet
Download MM74C373 Datasheet


MM74C373
October 1987
Revised January 1999
MM74C373 • MM74C374
3-STATE Octal D-Type Latch •
3-STATE Octal D-Type Flip-Flop
General Description
The MM74C373 and MM74C374 are integrated, comple-
mentary MOS (CMOS), 8-bit storage elements with 3-
STATE outputs. These outputs have been specially
designed to drive high capacitive loads, such as one might
find when driving a bus, and to have a fan out of 1 when
driving standard TTL. When a high logic level is applied to
the OUTPUT DISABLE input, all outputs go to a high
impedance state, regardless of what signals are present at
the other inputs and the state of the storage elements.
The MM74C373 is an 8-bit latch. When LATCH ENABLE is
high, the Q outputs will follow the D inputs. When LATCH
ENABLE goes low, data at the D inputs, which meets the
set-up and hold time requirements, will be retained at the
outputs until LATCH ENABLE returns high again.
The MM74C374 is an 8-bit, D-type, positive-edge triggered
flip-flop. Data at the D inputs, meeting the set-up and hold
time requirements, is transferred to the Q outputs on posi-
tive-going transitions of the CLOCK input.
Both the MM74C373 and the MM74C374 are being assem-
bled in 20-pin dual-in-line packages with 0.300” pin cen-
ters.
Features
s Wide supply voltage range: 3V to 15V
s High noise immunity: 0.45 VCC (typ.)
s Low power consumption
s TTL compatibility:
Fan out of 1driving standard TTL
s Bus driving capability
s 3-STATE outputs
s Eight storage elements in one package
s Single CLOCK/LATCH ENABLE and OUTPUT DIS-
ABLE control inputs
s 20-pin dual-in-line package with 0.300” centers takes
half the board space of a 24-pin package
Ordering Code:
Order Number Package Number
Package Description
MM74C373M
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74C373N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
MM74C374M
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74C374N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 1999 Fairchild Semiconductor Corporation DS005906.prf
www.fairchildsemi.com

MM74C373
Connection Diagrams
MM74C373
Pin Assignments for DIP and SOIC
MM74C374
Top View
Truth Tables
Output
Disable
L
L
L
H
MM74C373
LATCH
ENABLE
H
H
L
X
D
H
L
X
X
L = LOW logic level
H = HIGH logic level
X = Irrelevant
= LOW-to-HIGH logic level transition
Q = Preexisting output level
Hi-Z = High impedance output state
Q
H
L
Q
Hi-Z
Top View
Output
Disable
L
L
L
L
H
MM74C374
Clock
D
H
L
LX
HX
XX
Q
H
L
Q
Q
Hi-Z
www.fairchildsemi.com
2


Features MM74C373 • MM74C374 3-STATE Octal D-Ty pe Latch • 3-STATE Octal D-Type Flip- Flop October 1987 Revised January 1999 MM74C373 • MM74C374 3-STATE Octal D -Type Latch • 3-STATE Octal D-Type Fl ip-Flop General Description The MM74C37 3 and MM74C374 are integrated, compleme ntary MOS (CMOS), 8-bit storage element s with 3STATE outputs. These outputs ha ve been specially designed to drive hig h capacitive loads, such as one might f ind when driving a bus, and to have a f an out of 1 when driving standard TTL. When a high logic level is applied to t he OUTPUT DISABLE input, all outputs go to a high impedance state, regardless of what signals are present at the othe r inputs and the state of the storage e lements. The MM74C373 is an 8-bit latch . When LATCH ENABLE is high, the Q outp uts will follow the D inputs. When LATC H ENABLE goes low, data at the D inputs , which meets the set-up and hold time requirements, will be retained at the o utputs until LATCH ENABLE returns high again. The MM74C374 is an 8-bit,.
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