MM74C74 D Flip-Flop Datasheet

MM74C74 Datasheet, PDF, Equivalent


Part Number

MM74C74

Description

Dual D Flip-Flop

Manufacture

National

Total Page 6 Pages
Datasheet
Download MM74C74 Datasheet


MM74C74
MM54C74 MM74C74 Dual D Flip-Flop
General Description
The MM54C74 MM74C74 dual D flip-flop is a monolithic
complementary MOS (CMOS) integrated circuit constructed
with N- and P-channel enhancement transistors Each flip-
flop has independent data preset clear and clock inputs
and Q and Q outputs The logic level present at the data
input is transferred to the output during the positive going
transition of the clock pulse Preset or clear is independent
of the clock and accomplished by a low level at the preset
or clear input
Features
Y Supply voltage range
Y Tenth power TTL compatible
Y High noise immunity
3V to 15V
Drive 2 LPT2L loads
0 45 VCC (typ )
Y Low power
Y Medium speed operation
Applications
Y Automotive
Y Data terminals
Y Instrumentation
Y Medical electronics
Y Alarm system
Y Industrial electronics
Y Remote metering
Y Computers
Logic Diagram
February 1988
50 nW (typ )
10 MHz (typ )
with 10V supply
Truth Table
Preset Clear Qn
Qn
0 0 00
0 1 10
1 0 01
1 1 Qn Qn
No change in output from previous state
Order Number MM54C74 or MM74C74
C1995 National Semiconductor Corporation TL F 5885
Connection Diagram
Dual-In-Line Package
TL F 5885 – 1
Top View
Note A logic ‘‘0’’ on clear sets Q to logic ‘‘0’’
A logic ‘‘0’’ on preset sets Q to logic ‘‘1’’
TL F 5885 – 2
RRD-B30M105 Printed in U S A

MM74C74
Absolute Maximum Ratings (Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Voltage at Any Pin (Note 1)
Operating Temperature Range
MM54C74
MM74C74
b0 3V to VCC a0 3V
b55 C to a125 C
b40 C to a85 C
Storage Temperature Range
b65 C to a150 C
Power Dissipation
Dual-In-Line
Small Outline
700 mW
500 mW
Lead Temperature (Soldering 10 seconds)
260 C
Operating VCC Range
VCC(Max)
3V to 15V
18V
DC Electrical Characteristics Min Max limits apply across temperature range unless otherwise specified
Symbol
Parameter
Conditions
Min Typ Max Units
CMOS TO CMOS
VIN(1)
Logical ‘‘1’’ Input Voltage
VIN(0)
Logical ‘‘0’’ Input Voltage
VOUT(1)
Logical ‘‘1’’ Output Voltage
VOUT(0)
Logical ‘‘0’’ Output Voltage
IIN(1)
Logical ‘‘1’’ Input Current
IIN(0)
Logical ‘‘0’’ Input Current
ICC Supply Current
CMOS LPTTL INTERFACE
VCC e 5V
VCC e 10V
VCC e 5V
VCC e 10V
VCC e 5V
VCC e 10V
VCC e 5V
VCC e 10V
VCC e 15V
VCC e 15V
VCC e 15V
35
80
45
90
b1 0
15
20
05
10
10
0 05 60
V
V
V
V
V
V
V
V
mA
mA
mA
VIN(1)
Logical ‘‘1’’ Input Voltage
54C VCC e 4 5V
74C VCC e 4 75V
VIN(0)
Logical ‘‘0’’ Input Voltage
54C VCC e 4 75V
74C VCC e 4 75V
VOUT(1)
Logical ‘‘1’’ Output Voltage
54C VCC e 4 5V ID e b360 mA
74C VCC e 4 75V ID e b360 mA
VOUT(0)
Logical ‘‘0’’ Output Voltage
54C VCC e 4 5V ID e 360 mA
74C VCC e 4 75V ID e 360 mA
OUTPUT DRIVE (See 54C 74C Family Characteristics Data Sheet)
VCCb1 5
24
08 V
V
04 V
ISOURCE
Output Source Current
VCC e 5V VIN(0) e 0V
TA e 25 C VOUT e 0V
b1 75
mA
ISOURCE
Output Source Current
VCC e 10V VIN(0) e 0V
TA e 25 C VOUT e 0V
b8 0
mA
ISINK
Output Sink Current
VCC e 5V VIN(1) e 5V
TA e 25 C VOUT e VCC
1 75
mA
ISINK
Output Sink Current
VCC e 10V VIN(1) e 10V
TA e 25 C VOUT e VCC
80
mA
Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation
2


Features MM54C74 MM74C74 Dual D Flip-Flop Februa ry 1988 MM54C74 MM74C74 Dual D Flip-Fl op General Description The MM54C74 MM74 C74 dual D flip-flop is a monolithic co mplementary MOS (CMOS) integrated circu it constructed with N- and P-channel en hancement transistors Each flipflop has independent data preset clear and cloc k inputs and Q and Q outputs The logic level present at the data input is tran sferred to the output during the positi ve going transition of the clock pulse Preset or clear is independent of the c lock and accomplished by a low level at the preset or clear input Y Y Low pow er Medium speed operation 50 nW (typ ) 10 MHz (typ ) with 10V supply Applica tions Y Y Y Y Y Features Y Y Y Supply voltage range Tenth power TTL compatib le High noise immunity 3V to 15V Drive 2 LPT2L loads 0 45 VCC (typ ) Y Y Y Automotive Data terminals Instrumentati on Medical electronics Alarm system Ind ustrial electronics Remote metering Com puters Logic Diagram TL F 5885 – 1 Truth Table Preset 0 0 1 .
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