EXCLUSIVE-OR Gate. MM74C86 Datasheet


MM74C86 Gate. Datasheet pdf. Equivalent


MM74C86


Quad 2-Input EXCLUSIVE-OR Gate
MM74C86 Quad 2-Input EXCLUSIVE-OR Gate

October 1987 Revised January 1999

MM74C86 Quad 2-Input EXCLUSIVE-OR Gate
General Description
The MM74C86 employs complementary MOS (CMOS) transistors to achieve wide power supply operating range, low power consumption and high noise margin these gates provide basic functions used in the implementation of digital integrated circuit systems. The N- and P-channel enhancement mode transistors provide a symmetrical circuit with output swing essentially equal to the supply voltage. No DC power other than that caused by leakage current is consumed during static condition. All inputs are protected from damage due to static discharge by diode clamps to VCC and GND.

Features
s Wide supply voltage range: s Guaranteed noise margin: s High noise immunity: 3.0V to 15V 1.0V 0.45 VCC (typ.)

s Low power: TTL compatibility: Fan out of 2 driving 74L s Low power consumption: 10 nW/package (typ.) s The MM74C86 follows the MM74LS86 Pinout

Ordering Code:
Order Number MM74C86M MM74C86N Package Number M14A N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram
Pin Assignments for DIP and SOIC

Truth Table
Inputs A L L H H
H...



MM74C86
October 1987
Revised January 1999
MM74C86
Quad 2-Input EXCLUSIVE-OR Gate
General Description
The MM74C86 employs complementary MOS (CMOS)
transistors to achieve wide power supply operating range,
low power consumption and high noise margin these gates
provide basic functions used in the implementation of digi-
tal integrated circuit systems. The N- and P-channel
enhancement mode transistors provide a symmetrical cir-
cuit with output swing essentially equal to the supply volt-
age. No DC power other than that caused by leakage
current is consumed during static condition. All inputs are
protected from damage due to static discharge by diode
clamps to VCC and GND.
Features
s Wide supply voltage range: 3.0V to 15V
s Guaranteed noise margin: 1.0V
s High noise immunity: 0.45 VCC (typ.)
s Low power: TTL compatibility:
Fan out of 2 driving 74L
s Low power consumption: 10 nW/package (typ.)
s The MM74C86 follows the MM74LS86 Pinout
Ordering Code:
Order Number Package Number
Package Description
MM74C86M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
MM74C86N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Truth Table
Pin Assignments for DIP and SOIC
Inputs
AB
LL
LH
HL
HH
Output
Y
L
H
H
L
H = HIGH Level
L = LOW Level
Top View
© 1999 Fairchild Semiconductor Corporation DS005887.prf
www.fairchildsemi.com

MM74C86
Absolute Maximum Ratings(Note 1)
Voltage at any Pin (Note 1)
Operating Temperature Range
Storage Temperature Range
Power Dissipation (PD)
Dual-In-Line Package
Small Outline
Operating Range (VCC)
0.3V to VCC + 0.3V
40°C to +85°C
65°C to +150°C
700 mW
500 mW
3.0V to 15V
Absolute Maximum (VCC)
Lead Temperature
(Soldering, 10 seconds)
18V
260°C
Note 1: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. Except for “Operating Tempera-
ture Range” they are not meant to imply that the devices should be oper-
ated at these limits. The Electrical Characteristics table provides conditions
for actual device operation.
DC Electrical Characteristics
Min/max limits apply across temperature range unless otherwise noted
Symbol
Parameter
Conditions
CMOS TO CMOS
VIN(1)
Logical “1” Input Voltage
VIN(0)
Logical “0” Input Voltage
VOUT(1)
Logical “1” Output Voltage
VOUT(0)
Logical “0” Output Voltage
IIN(1)
Logical “1” Input Current
IIN(0)
Logical “0” Input Current
ICC Supply Current
CMOS/LPTTL INTERFACE
VCC = 5.0V
VCC = 10V
VCC = 5.0V
VCC = 10V
VCC = 5.0V, IO = −10 µA
VCC = 10V, IO = −10 µA
VCC = 5.0V, IO = +10 µA
VCC = 10V, IO = +10 µA
VCC = 15V, VIN = 15V
VCC = 15V, VIN = 0V
VCC = 15V
VIN(1)
Logical “1” Input Voltage
VCC = 4.75V
VIN(0)
Logical “0” Input Voltage
VCC = 4.75V
VOUT(1)
Logical “1” Output Voltage
VCC = 4.75V, IO = −360 µA
VOUT(0)
Logical “0” Output Voltage
VCC = 4.75V, IO = 360 µA
OUTPUT DRIVE (See Family Characteristics Data Sheet) (Short Circuit Current)
ISOURCE
ISOURCE
ISINK
ISINK
Output Source Current
(P-Channel)
Output Source Current
(P-Channel)
Output Sink Current
(N-Channel)
Output Sink Current
(N-Channel)
VCC = 5.0V, VOUT = 0V
TA = 25°C
VCC = 10V, VOUT = 0V
TA = 25°C
VCC = 5.0V, VOUT = VCC
TA = 25°C
VCC = 10V, VOUT = VCC
TA = 25°C
Min Typ
3.5
8.0
4.5
9.0
0.005
1.0 0.005
0.01
VCC1.5
2.4
1.75
8.0
1.75
8.0
3.3
15
3.6
16
Max
1.5
2.0
0.5
1.0
1.0
15
0.8
0.4
Units
V
V
V
V
V
V
V
V
µA
µA
µA
V
V
V
V
mA
mA
mA
mA
AC Electrical Characteristics (Note 2)
TA = 25°C, CL = 50 pF, unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tpd Propagation Time to Logical
VCC = 5.0V
110 185
ns
“1” or “0”
VCC = 10V
50 90 ns
CIN Input Capacitance
(Note 3)
5.0 pF
CPD Power Dissipation Capacitance
Per Gate (Note 4)
20 pF
Note 2: AC Parameters are guaranteed by DC correlated testing.
Note 3: Capacitance is guaranteed by periodic testing.
Note 4: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note—
AN-90.
www.fairchildsemi.com
2




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