MM74HC08 AND Gate Datasheet

MM74HC08 Datasheet, PDF, Equivalent


Part Number

MM74HC08

Description

Quad 2-Input AND Gate

Manufacture

Fairchild

Total Page 7 Pages
Datasheet
Download MM74HC08 Datasheet


MM74HC08
September 1983
Revised December 1999
MM74HC08
Quad 2-Input AND Gate
General Description
The MM74HC08 AND gates utilize advanced silicon-gate
CMOS technology to achieve operating speeds similar to
LS-TTL gates with the low power consumption of standard
CMOS integrated circuits. The HC08 has buffered outputs,
providing high noise immunity and the ability to drive 10
LS-TTL loads. The 74HC logic family is functionally as well
as pin-out compatible with the standard 74LS logic family.
All inputs are protected from damage due to static dis-
charge by internal diode clamps to VCC and ground.
Features
s Typical propagation delay: 7 ns (tPHL), 12 ns (tPLH)
s Fanout of 10 LS-TTL loads
s Quiescent power consumption: 2 µA maximum at room
temperature
s Low input current: 1 µA maximum
Ordering Code:
Order Number Package Number
Package Description
MM74HC08M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Wide
MM74HC08SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC08MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC08N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. (Tape and Reel not available in N14A)
Connection Diagram
Top View
© 1999 Fairchild Semiconductor Corporation DS005297
www.fairchildsemi.com

MM74HC08
Absolute Maximum Ratings(Note 1)
(Note 2)
Supply Voltage (VCC)
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (IIK, IOK)
DC Output Current, per pin (IOUT)
DC VCC or GND Current, per pin
(ICC)
Storage Temperature Range (TSTG)
Power Dissipation (PD)
(Note 3)
S.O. Package only
Lead Temperature (TL)
(Soldering 10 seconds)
0.5 to +7.0V
1.5 to VCC +1.5V
0.5 to VCC +0.5V
±20 mA
±25 mA
±50 mA
65°C to +150°C
600 mW
500 mW
260°C
Recommended Operating
Conditions
Min Max Units
Supply Voltage (VCC)
DC Input or Output Voltage
(VIN, VOUT)
Operating Temperature Range (TA)
Input Rise or Fall Times
2
0
40
6
VCC
+85
V
V
°C
(tr, tf) VCC = 2.0V
1000 ns
VCC = 4.5V
500 ns
VCC = 6.0V
400 ns
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating — plastic “N” package:
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
VCC TA = 25°C
Typ
TA = −40 to 85°C TA = −40 to 125°C Units
Guaranteed Limits
VIH Minimum HIGH Level
Input Voltage
2.0V
4.5V
1.5
3.15
1.5
3.15
1.5
3.15
V
V
6.0V
4.2 4.2
4.2 V
VIL Maximum LOW Level
Input Voltage
2.0V
4.5V
0.5
1.35
0.5
1.35
0.5
1.35
V
V
6.0V
1.8 1.8
1.8 V
VOH Minimum HIGH Level
Output Voltage
VIN = VIH
|IOUT| 20 µA
2.0V
4.5V
2.0
4.5
1.9
4.4
1.9
4.4
1.9 V
4.4 V
6.0V
6.0
5.9
5.9
5.9 V
VOL Maximum LOW Level
Output Voltage
VIN = VIH
|IOUT| 4.0 mA
|IOUT| 5.2 mA
VIN = VIH or VIL
|IOUT| 20 µA
4.5V
6.0V
2.0V
4.5V
4.2
5.7
0
0
3.98
5.48
0.1
0.1
3.84
5.34
0.1
0.1
3.7 V
5.2 V
0.1 V
0.1 V
6.0V
0
0.1
0.1
0.1 V
VIN = VIH or VIL
|IOUT| 4.0 mA
4.5V
0.2
0.26
0.33
0.4 V
|IOUT| 5.2 mA
6.0V
0.2
0.26
0.33
0.4 V
IIN Maximum Input Current
VIN = VCC or GND 6.0V
±0.1
±1.0
±1.0
µA
ICC Maximum Quiescent Supply Current VIN = VCC or GND 6.0V
2.0 20
40 µA
IOUT = 0 µA
Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage cur-
rent (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
www.fairchildsemi.com
2


Features MM74HC08 Quad 2-Input AND Gate Septembe r 1983 Revised December 1999 MM74HC08 Quad 2-Input AND Gate General Descripti on The MM74HC08 AND gates utilize advan ced silicon-gate CMOS technology to ach ieve operating speeds similar to LS-TTL gates with the low power consumption o f standard CMOS integrated circuits. Th e HC08 has buffered outputs, providing high noise immunity and the ability to drive 10 LS-TTL loads. The 74HC logic f amily is functionally as well as pin-ou t compatible with the standard 74LS log ic family. All inputs are protected fro m damage due to static discharge by int ernal diode clamps to VCC and ground. Features s Typical propagation delay: 7 ns (tPHL), 12 ns (tPLH) s Fanout of 10 LS-TTL loads s Quiescent power consump tion: 2 µA maximum at room temperature s Low input current: 1 µA maximum Or dering Code: Order Number MM74HC08M MM7 4HC08SJ MM74HC08MTC MM74HC08N Package N umber M14A M14D MTC14 N14A Package Desc ription 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS.
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