MM74HC11 AND Gate Datasheet

MM74HC11 Datasheet, PDF, Equivalent


Part Number

MM74HC11

Description

Triple 3-Input AND Gate

Manufacture

National

Total Page 5 Pages
Datasheet
Download MM74HC11 Datasheet


MM74HC11
January 1988
MM54HC11 MM74HC11
Triple 3-Input AND Gate
General Description
These AND gates utilize advanced silicon-gate CMOS tech-
nology to achieve operating speeds similar to LS-TTL gates
with the low power consumption of standard CMOS inte-
grated circuits All gates have buffered outputs providing
high noise immunity and the ability to drive 10 LS-TTL loads
The 54HC 74HC logic family is functionally as well as pin-
out compatible with the standard 54LS 74LS logic family
All inputs are protected from damage due to static dis-
charge by internal diode clamps to VCC and ground
Features
Y Typical propagation delay 12 ns
Y Wide power supply range 2 – 6V
Y Low quiescent current 20 mA maximum (74HC Series)
Y Low input current 1 mA maximum
Y Fanout of 10 LS-TTL loads
Connection and Logic Diagrams
Dual-In-Line Package
Top View
Order Number MM54HC11 or MM74HC11
TL F 5298 – 1
(1 OF 3 GATES)
TL F 5298 – 2
C1995 National Semiconductor Corporation TL F 5298
RRD-B30M105 Printed in U S A

MM74HC11
Absolute Maximum Ratings (Notes 1 2)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage (VCC)
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (IIK IOK)
DC Output Current per pin (IOUT)
DC VCC or GND Current per pin (ICC)
Storage Temperature Range (TSTG)
Power Dissipation (PD)
(Note 3)
S O Package only
b0 5 to a7 0V
b1 5 to VCCa1 5V
b0 5 to VCCa0 5V
g20 mA
g25 mA
g50 mA
b65 C to a150 C
600 mW
500 mW
Lead Temperature (TL)
(Soldering 10 seconds)
260 C
Operating Conditions
Supply Voltage (VCC)
DC Input or Output Voltage
(VIN VOUT)
Operating Temp Range (TA)
MM74HC
MM54HC
Min
2
0
b40
b55
Input Rise or Fall Times
(tr tf)
VCCe2 0V
VCCe4 5V
VCCe6 0V
Max
6
VCC
a85
a125
1000
500
400
Units
V
V
C
C
ns
ns
ns
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
VCC
TAe25 C
Typ
74HC
54HC
TAeb40 to 85 C TAeb55 to 125 C
Guaranteed Limits
Units
VIH Minimum High Level
Input Voltage
2 0V
4 5V
6 0V
15 15
3 15 3 15
42 42
15 V
3 15 V
42 V
VIL Maximum Low Level
Input Voltage
2 0V
4 5V
6 0V
05 05
1 35 1 35
18 18
05 V
1 35 V
18 V
VOH
Minimum High Level VINeVIH
Output Voltage
lIOUTls20 mA
2 0V 2 0 1 9
4 5V 4 5 4 4
6 0V 6 0 5 9
19
44
59
19 V
44 V
59 V
VINeVIH
lIOUTls4 0 mA
lIOUTls5 2 mA
4 5V 4 2 3 98
6 0V 5 7 5 48
VOL Maximum Low Level VINeVIH or VIL
Output Voltage
lIOUTls20 mA
2 0V 0 0 1
4 5V 0 0 1
6 0V 0 0 1
3 84
5 34
01
01
01
37 V
52 V
01 V
01 V
01 V
VINeVIH or VIL
lIOUTls4 0 mA
lIOUTls5 2 mA
4 5V 0 2 0 26
6 0V 0 2 0 26
IIN Maximum Input VINeVCC or GND 6 0V
Current
g0 1
0 33
0 33
g1 0
04
04
g1 0
V
V
mA
ICC Maximum Quiescent VINeVCC or GND 6 0V 2 0 20
Supply Current
IOUTe0 mA
40 mA
Note 1 Absolute Maximum Ratings are those values beyond which damage to the device may occur
Note 2 Unless otherwise specified all voltages are referenced to ground
Note 3 Power Dissipation temperature derating plastic ‘‘N’’ package b12 mW C from 65 C to 85 C ceramic ‘‘J’’ package b12 mW C from 100 C to 125 C
Note 4 For a power supply of 5V g10% the worst case output voltages (VOH and VOL) occur for HC at 4 5V Thus the 4 5V values should be used when designing
with this supply Worst case VIH and VIL occur at VCCe5 5V and 4 5V respectively (The VIH value at 5 5V is 3 85V ) The worst case leakage current (IIN ICC and
IOZ) occur for CMOS at the higher voltage and so the 6 0V values should be used
VIL limits are currently tested at 20% of VCC The above VIL specification (30% of VCC) will be implemented no later than Q1 CY’89
2


Features MM54HC11 MM74HC11 Triple 3-Input AND Gat e January 1988 MM54HC11 MM74HC11 Trip le 3-Input AND Gate General Description These AND gates utilize advanced silic on-gate CMOS technology to achieve oper ating speeds similar to LS-TTL gates wi th the low power consumption of standar d CMOS integrated circuits All gates ha ve buffered outputs providing high nois e immunity and the ability to drive 10 LS-TTL loads The 54HC 74HC logic family is functionally as well as pinout comp atible with the standard 54LS 74LS logi c family All inputs are protected from damage due to static discharge by inter nal diode clamps to VCC and ground Fea tures Y Y Y Y Y Typical propagation de lay 12 ns Wide power supply range 2 – 6V Low quiescent current 20 mA maximum (74HC Series) Low input current 1 mA m aximum Fanout of 10 LS-TTL loads Conne ction and Logic Diagrams Dual-In-Line P ackage TL F 5298 – 1 Top View Order Number MM54HC11 or MM74HC11 TL F 5298 – 2 (1 OF 3 GATES) C1995 National Semiconductor Corporation TL .
Keywords MM74HC11, datasheet, pdf, National, Triple, 3-Input, AND, Gate, M74HC11, 74HC11, 4HC11, MM74HC1, MM74HC, MM74H, Equivalent, stock, pinout, distributor, price, schematic, inventory, databook, Electronic, Components, Parameters, parts, cross reference, chip, Semiconductor, circuit, Electric, manual, substitute




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