Line Decoder. MM74HC138 Datasheet


MM74HC138 Decoder. Datasheet pdf. Equivalent


Part Number

MM74HC138

Description

3-to-8 Line Decoder

Manufacture

Fairchild

Total Page 7 Pages
Datasheet
Download MM74HC138 Datasheet


MM74HC138
September 1983
Revised February 1999
MM74HC138
3-to-8 Line Decoder
General Description
The MM74HC138 decoder utilizes advanced silicon-gate
CMOS technology and is well suited to memory address
decoding or data routing applications. The circuit features
high noise immunity and low power consumption usually
associated with CMOS circuitry, yet has speeds compara-
ble to low power Schottky TTL logic.
The MM74HC138 has 3 binary select inputs (A, B, and C).
If the device is enabled, these inputs determine which one
of the eight normally HIGH outputs will go LOW. Two active
LOW and one active HIGH enables (G1, G2A and G2B)
are provided to ease the cascading of decoders.
The decoder’s outputs can drive 10 low power Schottky
TTL equivalent loads, and are functionally and pin equiva-
lent to the 74LS138. All inputs are protected from damage
due to static discharge by diodes to VCC and ground.
Features
s Typical propagation delay: 20 ns
s Wide power supply range: 2V–6V
s Low quiescent current: 80 µA maximum (74HC Series)
s Low input current: 1 µA maximum
s Fanout of 10 LS-TTL loads
Ordering Code:
Order Number Package Number
Package Description
MM74HC138M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74HC138SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC138MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC138N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignment for DIP, SOIC, SOP and TSSOP
© 1999 Fairchild Semiconductor Corporation DS005120.prf
www.fairchildsemi.com

MM74HC138
Truth Table
Inputs
Enable
Select
G1 G2 (Note 1) C B A
X H XXX
L X XXX
H L LLL
H L LLH
H L LHL
H L LHH
H L HLL
H L HLH
H L HH L
H L HHH
H = HIGH Level, L = LOW Level, X = don’t care
Note 1: G2 = G2A+G2B
Logic Diagram
Outputs
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
HHHHHHHH
HHHHHHHH
L HHHHHHH
H L HHHHHH
HH LHHHHH
HHH LHHHH
HHHH L HHH
HHHHH LHH
HHHHHH LH
HHHHHHH L
www.fairchildsemi.com
2


Features MM74HC138 3-to-8 Line Decoder September 1983 Revised February 1999 MM74HC138 3-to-8 Line Decoder General Description The MM74HC138 decoder utilizes advance d silicon-gate CMOS technology and is w ell suited to memory address decoding o r data routing applications. The circui t features high noise immunity and low power consumption usually associated wi th CMOS circuitry, yet has speeds compa rable to low power Schottky TTL logic. The MM74HC138 has 3 binary select input s (A, B, and C). If the device is enabl ed, these inputs determine which one of the eight normally HIGH outputs will g o LOW. Two active LOW and one active HI GH enables (G1, G2A and G2B) are provid ed to ease the cascading of decoders. T he decoder’s outputs can drive 10 low power Schottky TTL equivalent loads, a nd are functionally and pin equivalent to the 74LS138. All inputs are protecte d from damage due to static discharge b y diodes to VCC and ground. Features s Typical propagation delay: 20 ns s Wide power supply range: 2V–6.
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