Line Decoder. MM74HC139 Datasheet


MM74HC139 Decoder. Datasheet pdf. Equivalent


Part Number

MM74HC139

Description

Dual 2-To-4 Line Decoder

Manufacture

Fairchild

Total Page 7 Pages
Datasheet
Download MM74HC139 Datasheet


MM74HC139
September 1983
Revised February 1999
MM74HC139
Dual 2-To-4 Line Decoder
General Description
The MM74HC139 decoder utilizes advanced silicon-gate
CMOS technology, and is well suited to memory address
decoding or data routing applications. It possesses the
high noise immunity and low power consumption usually
associated with CMOS circuitry, yet has speeds compara-
ble to low power Schottky TTL logic.
The MM74HC139 contain two independent one-of-four
decoders each with a single active low enable input (G1, or
G2). Data on the select inputs (A1, and B1 or A2, and B2)
cause one of the four normally high outputs to go LOW.
The decoder’s outputs can drive 10 low power Schottky
TTL equivalent loads, and are functionally as well as pin
equivalent to the 74LS139. All inputs are protected from
damage due to static discharge by diodes to VCC and
ground.
Features
s Typical propagation delays —
Select to outputs (4 delays): 18 ns
Select to output (5 delays): 28 ns
Enable to output: 20 ns
s Low power: 40 µW quiescent supply power
s Fanout of 10 LS-TTL devices
s Input current maximum 1 µA, typical 10 pA
Ordering Code:
Order Number Package Number
Package Description
MM74HC139M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74HC139SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC139MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP) JEDEC MO-153, 4.4mm Wide
MM74HC139N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Truth Table
Pin Assignments for DIP, SOIC, SOP and TSSOP
Inputs
Enable Select
G BA
H XX
L LL
L LH
L HL
L HH
H = HIGH Level
L = LOW Level
X = Don't Care
Outputs
Y0 Y1 Y2 Y3
HHHH
L HHH
H LHH
HH L H
HHHL
© 1999 Fairchild Semiconductor Corporation DS005311.prf
www.fairchildsemi.com

MM74HC139
Logic Diagram
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2


Features MM74HC139 Dual 2-To-4 Line Decoder Sept ember 1983 Revised February 1999 MM74H C139 Dual 2-To-4 Line Decoder General D escription The MM74HC139 decoder utiliz es advanced silicon-gate CMOS technolog y, and is well suited to memory address decoding or data routing applications. It possesses the high noise immunity a nd low power consumption usually associ ated with CMOS circuitry, yet has speed s comparable to low power Schottky TTL logic. The MM74HC139 contain two indepe ndent one-of-four decoders each with a single active low enable input (G1, or G2). Data on the select inputs (A1, and B1 or A2, and B2) cause one of the fou r normally high outputs to go LOW. The decoder’s outputs can drive 10 low po wer Schottky TTL equivalent loads, and are functionally as well as pin equival ent to the 74LS139. All inputs are prot ected from damage due to static dischar ge by diodes to VCC and ground. Featur es s Typical propagation delays — Sel ect to outputs (4 delays): 18 ns Select to output (5 delays): 28 ns.
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