MM74HC14 Schmitt Trigger Datasheet

MM74HC14 Datasheet, PDF, Equivalent


Part Number

MM74HC14

Description

Hex Inverting Schmitt Trigger

Manufacture

Fairchild

Total Page 8 Pages
Datasheet
Download MM74HC14 Datasheet


MM74HC14
September 1983
Revised May 2005
MM74HC14
Hex Inverting Schmitt Trigger
General Description
The MM74HC14 utilizes advanced silicon-gate CMOS
technology to achieve the low power dissipation and high
noise immunity of standard CMOS, as well as the capability
to drive 10 LS-TTL loads.
The 74HC logic family is functionally and pinout compatible
with the standard 74LS logic family. All inputs are protected
from damage due to static discharge by internal diode
clamps to VCC and ground.
Features
s Typical propagation delay: 13 ns
s Wide power supply range: 2–6V
s Low quiescent current: 20 PA maximum (74HC Series)
s Low input current: 1 PA maximum
s Fanout of 10 LS-TTL loads
s Typical hysteresis voltage: 0.9V at VCC 4.5V
Ordering Code:
Order Number
Package
Number
Package Description
MM74HC14M
M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
MM74HC14MX_NL
M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
MM74HC14SJ
M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC14MTC
MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC14MTCX_NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
MM74HC14N
N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
MM74HC14N_NL
N14A Pb-Free 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Connection Diagram
Logic Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
© 2005 Fairchild Semiconductor Corporation DS005105
www.fairchildsemi.com

MM74HC14
Absolute Maximum Ratings(Note 1)
(Note 2)
Supply Voltage (VCC)
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (IIK, IOK)
DC Output Current, per pin (IOUT)
DC VCC or GND Current, per pin
(ICC)
Storage Temperature Range (TSTG)
Power Dissipation (PD)
(Note 3)
S.O. Package only
Lead Temperature (TL)
(Soldering 10 seconds)
0.5 to 7.0V
1.5 to VCC 1.5V
0.5 to VCC 0.5V
r20 mA
r25 mA
r50 mA
65qC to 150qC
600 mW
500 mW
260qC
Recommended Operating
Conditions
Supply Voltage (VCC)
DC Input or Output Voltage
(VIN, VOUT)
Operating Temperature Range (TA)
Min Max Units
26V
0 VCC V
55 125 qC
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating plastic Npackage: 
12 mW/qC from 65qC to 85qC.
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
VCC
TA 25qC
TA 40 to 85qC TA 55 to 125qC Units
Typ Guaranteed Limits
VT Positive Going
Minimum
Threshold Voltage
2.0V
4.5V
1.2
2.7
1.0
2.0
1.0
2.0
1.0 V
2.0 V
6.0V
3.2
3.0
3.0
3.0 V
Maximum
2.0V
1.2
1.5
1.5
1.5 V
4.5V 2.7 3.15
3.15
3.15 V
6.0V
3.2
4.2
4.2
4.2 V
VT Negative Going
Minimum
Threshold Voltage
2.0V
4.5V
0.7
1.8
0.3
0.9
0.3
0.9
0.3 V
0.9 V
6.0V
2.2
1.2
1.2
1.2 V
Maximum
2.0V
0.7
1.0
1.0
1.0 V
4.5V
1.8
2.2
2.2
2.2 V
6.0V
2.2
3.0
3.0
3.0 V
VH
Hysteresis Voltage
Minimum
2.0V
4.5V
0.5
0.9
0.2
0.4
0.2
0.4
0.2 V
0.4 V
6.0V
1.0
0.5
0.5
0.5 V
Maximum
2.0V
0.5
1.0
1.0
1.0 V
4.5V
0.9
1.4
1.4
1.4 V
6.0V
1.0
1.5
1.5
1.5 V
VOH Minimum HIGH Level VIN VIL
Output Voltage
|IOUT| 20 PA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9 V
4.4 V
5.9 V
VIN VIL
|IOUT| 4.0 mA
|IOUT| 5.2 mA
VOL Maximum LOW Level VIN VIH
Output Voltage
|IOUT| 20 PA
4.5V 4.2 3.98
6.0V 5.7 5.48
2.0V
0
0.1
4.5V
0
0.1
6.0V
0
0.1
3.84
5.34
0.1
0.1
0.1
3.7 V
5.2 V
0.1 V
0.1 V
0.1 V
VIN VIH
|IOUT| 4.0 mA
4.5V 0.2 0.26
0.33
0.4 V
|IOUT| 5.2 mA
6.0V 0.2 0.26
0.33
0.4 V
IIN Maximum Input Current VIN VCC or GND
6.0V
r0.1 r1.0
r1.0 PA
ICC Maximum Quiescent VIN VCC or GND
6.0V
2.0 20
40 PA
Supply Current
IOUT 0 PA
Note 4: For a power supply of 5V r10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case VIH and VIL occur at VCC 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage cur-
rent (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
www.fairchildsemi.com
2


Features MM74HC14 Hex Inverting Schmitt Trigger September 1983 Revised February 1999 M M74HC14 Hex Inverting Schmitt Trigger G eneral Description The MM74HC14 utilize s advanced silicon-gate CMOS technology to achieve the low power dissipation a nd high noise immunity of standard CMOS , as well as the capability to drive 10 LS-TTL loads. The 74HC logic family is functionally and pinout compatible wit h the standard 74LS logic family. All i nputs are protected from damage due to static discharge by internal diode clam ps to VCC and ground. Features s Typic al propagation delay: 13 ns s Wide powe r supply range: 2–6V s Low quiescent current: 20 µA maximum (74HC Series) s Low input current: 1 µA maximum s Fan out of 10 LS-TTL loads s Typical hyster esis voltage: 0.9V at VCC = 4.5V Order ing Code: Order Number MM74HC14M MM74HC 14SJ MM74HC14MTC MM74HC14N Package Numb er M14A M14D MTC14 N14A Package Descrip tion 14-Lead Small Outline Integrated C ircuit (SOIC), JEDEC MS-120, 0.150” Narrow 14-Lead Small Outline Pa.
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