MM74HC151 Digital Multiplexer Datasheet

MM74HC151 Datasheet, PDF, Equivalent


Part Number

MM74HC151

Description

8-Channel Digital Multiplexer

Manufacture

Fairchild

Total Page 7 Pages
Datasheet
Download MM74HC151 Datasheet


MM74HC151
September 1983
Revised February 1999
MM74HC151
8-Channel Digital Multiplexer
General Description
The MM74HC151 high speed Digital multiplexer utilizes
advanced silicon-gate CMOS technology. Along with the
high noise immunity and low power dissipation of standard
CMOS integrated circuits, it possesses the ability to drive
10 LS-TTL loads. The MM74HC151 selects one of the 8
data sources, depending on the address presented on the
A, B, and C inputs. It features both true (Y) and comple-
ment (W) outputs. The STROBE input must be at a low
logic level to enable this multiplexer. A high logic level at
the STROBE forces the W output HIGH and the Y output
LOW.
The 74HC logic family is functionally as well as pin-out
compatible with the standard 74LS logic family. All inputs
are protected from damage due to static discharge by inter-
nal diode clamps to VCC and ground.
Features
s Typical propagation delay data select to output Y: 26 ns
s Wide operating supply voltage range: 2–6V
s Low input current: 1 µA maximum
s Low quiescent supply current: 80 µA maximum (74HC)
s High output drive current: 4 mA minimum
Ordering Code:
Order Number Package Number
Package Description
MM74HC151M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74HC151SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC151MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC151N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Truth Table
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
Inputs
Select
Strobe
CBA
S
XXX
H
LLL
L
L LH
L
LHL
L
L HH
L
HLL
L
HLH
L
HHL
L
HHH
L
Outputs
YW
LH
D0 D0
D1 D1
D2 D2
D3 D3
D4 D4
D5 D5
D6 D6
D7 D7
H = HIGH Level, L = LOW Level, X = Don't Care
D0, D1...D7 = the level of the respective D input
© 1999 Fairchild Semiconductor Corporation DS005313.prf
www.fairchildsemi.com

MM74HC151
Logic Diagram
www.fairchildsemi.com
2


Features MM74HC151 8-Channel Digital Multiplexer September 1983 Revised February 1999 MM74HC151 8-Channel Digital Multiplexer General Description The MM74HC151 high speed Digital multiplexer utilizes adv anced silicon-gate CMOS technology. Alo ng with the high noise immunity and low power dissipation of standard CMOS int egrated circuits, it possesses the abil ity to drive 10 LS-TTL loads. The MM74H C151 selects one of the 8 data sources, depending on the address presented on the A, B, and C inputs. It features bot h true (Y) and complement (W) outputs. The STROBE input must be at a low logic level to enable this multiplexer. A hi gh logic level at the STROBE forces the W output HIGH and the Y output LOW. Th e 74HC logic family is functionally as well as pin-out compatible with the sta ndard 74LS logic family. All inputs are protected from damage due to static di scharge by internal diode clamps to VCC and ground. Features s Typical propag ation delay data select to output Y: 26 ns s Wide operating sup.
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