Line Decoder. MM74HC154 Datasheet


MM74HC154 Decoder. Datasheet pdf. Equivalent


MM74HC154


4-to-16 Line Decoder
MM74HC154 4-to-16 Line Decoder

September 1983 Revised February 1999

MM74HC154 4-to-16 Line Decoder
General Description
The MM74HC154 decoder utilizes advanced silicon-gate CMOS technology, and is well suited to memory address decoding or data routing applications. It possesses high noise immunity, and low power consumption of CMOS with speeds similar to low power Schottky TTL circuits. The MM74HC154 have 4 binary select inputs (A, B, C, and D). If the device is enabled these inputs determine which one of the 16 normally HIGH outputs will go LOW. Two active LOW enables (G1 and G2) are provided to ease cascading of decoders with little or no external logic. Each output can drive 10 low power Schottky TTL equivalent loads, and is functionally and pin equivalent to the 74LS154. All inputs are protected from damage due to static discharge by diodes to VCC and ground.

Features
s Typical propagation delay: 21 ns s Power supply quiescent current: 80 µA s Wide power supply voltage range: 2–6V s Low input current: 1 µA maximum

Ordering Code:
Order Number MM74HC154WM MM74HC154MTC MM74HC154N Package Number M24B MTC24 N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide

Devices also availab...



MM74HC154
September 1983
Revised February 1999
MM74HC154
4-to-16 Line Decoder
General Description
The MM74HC154 decoder utilizes advanced silicon-gate
CMOS technology, and is well suited to memory address
decoding or data routing applications. It possesses high
noise immunity, and low power consumption of CMOS with
speeds similar to low power Schottky TTL circuits.
The MM74HC154 have 4 binary select inputs (A, B, C, and
D). If the device is enabled these inputs determine which
one of the 16 normally HIGH outputs will go LOW. Two
active LOW enables (G1 and G2) are provided to ease
cascading of decoders with little or no external logic.
Each output can drive 10 low power Schottky TTL equiva-
lent loads, and is functionally and pin equivalent to the
74LS154. All inputs are protected from damage due to
static discharge by diodes to VCC and ground.
Features
s Typical propagation delay: 21 ns
s Power supply quiescent current: 80 µA
s Wide power supply voltage range: 2–6V
s Low input current: 1 µA maximum
Ordering Code:
Order Number Package Number
Package Description
MM74HC154WM
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
MM74HC154MTC
MTC24
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC154N
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Truth Table
Pin Assignments for DIP, SOIC and TSSOP
Top View
Inputs
Low
G1 G2 D C B A Output
(Note 1)
LLLLLL
0
L L L L LH
1
L L L LHL
2
L L L LHH
3
L L LHL L
4
L L LHLH
5
L L LHHL
6
L L LHHH
7
L LHL L L
8
L LHL LH
9
L L H L H L 10
L L H L H H 11
L L H H L L 12
L L H H L H 13
L L H H H L 14
L L H H H H 15
LHXXXX —
HLXXXX —
HHXXXX —
Note 1: All others HIGH
© 1999 Fairchild Semiconductor Corporation DS005122.prf
www.fairchildsemi.com

MM74HC154
Logic Diagram
www.fairchildsemi.com
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