MM74HC164 Shift Register Datasheet

MM74HC164 Datasheet, PDF, Equivalent


Part Number

MM74HC164

Description

8-Bit Serial-in/Parallel-out Shift Register

Manufacture

Fairchild

Total Page 8 Pages
Datasheet
Download MM74HC164 Datasheet


MM74HC164
February 2008
MM74HC164
8-Bit Serial-in/Parallel-out Shift Register
Features
Typical operating frequency: 50MHz
Typical propagation delay: 19ns (clock to Q)
Wide operating supply voltage range: 2V to 6V
Low input current: 1µA maximum
Low quiescent supply current: 80µA maximum
(74HC Series)
Fanout of 10 LS-TTL loads
General Description
The MM74HC164 utilizes advanced silicon-gate CMOS
technology. It has the high noise immunity and low con-
sumption of standard CMOS integrated circuits. It also
offers speeds comparable to low power Schottky
devices.
This 8-bit shift register has gated serial inputs and
CLEAR. Each register bit is a D-type master/slave flip-
flop. Inputs A & B permit complete control over the
incoming data. A LOW at either or both inputs inhibits
entry of new data and resets the first flip-flop to the low
level at the next clock pulse. A high level on one input
enables the other input which will then determine the
state of the first flip-flop. Data at the serial inputs may be
changed while the clock is HIGH or LOW, but only infor-
mation meeting the setup and hold time requirements
will be entered. Data is serially shifted in and out of the
8-bit register during the positive going transition of the
clock pulse. Clear is independent of the clock and
accomplished by a low level at the CLEAR input.
The 74HC logic family is functionally as well as pin-out
compatible with the standard 74LS logic family. All inputs
are protected from damage due to static discharge by
internal diode clamps to VCC and ground.
Ordering Information
Order Number
Package
Number
Package Description
MM74HC164M
MM74HC164MTC
MM74HC164N
M14A
MTC14
N14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1983 Fairchild Semiconductor Corporation
MM74HC164 Rev. 1.5.0
www.fairchildsemi.com

MM74HC164
Connection Diagram
Top View
Logic Diagram
Truth Table
Inputs
Outputs
Clear Clock A B QA
L X XX L
QB ... QH
L ... L
H L X X QAO QBO ... QHO
H
HH H
QAn ... QGn
H L X L QA ... QGn
H
XL L
QAn ... QGn
H = HIGH Level (steady state)
L = LOW Level (steady state)
X = Irrelevant (any input, including transitions)
↑ = Transition from LOW-to-HIGH level.
QAO, QBO, QHO = the level of QA, QB, or QH,
respectively, before the indicated steady state input
conditions were established.
QAn, QGn = The level of QA or QG before the most
recent transition of the clock; indicated a one-bit shift.
©1983 Fairchild Semiconductor Corporation
MM74HC164 Rev. 1.5.0
2
www.fairchildsemi.com


Features MM74HC164 8-Bit Serial-in/Parallel-out S hift Register September 1983 Revised F ebruary 1999 MM74HC164 8-Bit Serial-in /Parallel-out Shift Register General De scription The MM74HC164 utilizes advanc ed silicon-gate CMOS technology. It has the high noise immunity and low consum ption of standard CMOS integrated circu its. It also offers speeds comparable t o low power Schottky devices. This 8-Bi t shift register has gated serial input s and CLEAR. Each register bit is a D-t ype master/slave flip-flop. Inputs A & B permit complete control over the inco ming data. A LOW at either or both inpu ts inhibits entry of new data and reset s the first flip-flop to the low level at the next clock pulse. A high level o n one input enables the other input whi ch will then determine the state of the first flip-flop. Data at the serial in puts may be changed while the clock is HIGH or LOW, but only information meeti ng the setup and hold time requirements will be entered. Data is serially shifted in and out of the 8-.
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