3-STATE Multiplexer. MM74HC251 Datasheet


MM74HC251 Multiplexer. Datasheet pdf. Equivalent


MM74HC251


8-Channel 3-STATE Multiplexer
MM74HC251 8-Channel 3-STATE Multiplexer

September 1983 Revised February 1999

MM74HC251 8-Channel 3-STATE Multiplexer
General Description
The MM74HC251 8-channel digital multiplexer with 3STATE outputs utilizes advanced silicon-gate CMOS technology. Along with the high noise immunity and low power consumption of standard CMOS integrated circuits, it possesses the ability to drive 10 LS-TTL loads. The large output drive capability and 3-STATE feature make this part ideally suited for interfacing with bus lines in a bus oriented system. This multiplexer features both true (Y) and complement (W) outputs as well as a STROBE input. The STROBE must be at a low logic level to enable this device. When the STROBE input is HIGH, both outputs are in the high impedance state. When enabled, address information on the data select inputs determines which data input is routed to the Y and W outputs. The 74HC logic family is speed, function, as well as pinout compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground.

Features
s Typical propagation delay Data select to Y: 26 ns s Wide supply range: 2–6V s Low power supply quiescent current: 80 µA maximum (74HC) s 3-STATE outputs for interface to bus oriented systems

Ordering Code:
Order Number MM74HC251M MM74HC251SJ MM74HC251MTC MM74HC251N Package Nu...



MM74HC251
September 1983
Revised February 1999
MM74HC251
8-Channel 3-STATE Multiplexer
General Description
The MM74HC251 8-channel digital multiplexer with 3-
STATE outputs utilizes advanced silicon-gate CMOS tech-
nology. Along with the high noise immunity and low power
consumption of standard CMOS integrated circuits, it pos-
sesses the ability to drive 10 LS-TTL loads. The large out-
put drive capability and 3-STATE feature make this part
ideally suited for interfacing with bus lines in a bus oriented
system.
This multiplexer features both true (Y) and complement
(W) outputs as well as a STROBE input. The STROBE
must be at a low logic level to enable this device. When the
STROBE input is HIGH, both outputs are in the high
impedance state. When enabled, address information on
the data select inputs determines which data input is routed
to the Y and W outputs. The 74HC logic family is speed,
function, as well as pinout compatible with the standard
74LS logic family. All inputs are protected from damage
due to static discharge by internal diode clamps to VCC and
ground.
Features
s Typical propagation delay
Data select to Y: 26 ns
s Wide supply range: 2–6V
s Low power supply quiescent current:
80 µA maximum (74HC)
s 3-STATE outputs for interface to bus oriented
systems
Ordering Code:
Order Number Package Number
Package Description
MM74HC251M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
MM74HC251SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC251MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC251N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
© 1999 Fairchild Semiconductor Corporation DS005328.prf
www.fairchildsemi.com

MM74HC251
Truth Table
Inputs
Select
CBA
XXX
LLL
L LH
LHL
L HH
HL L
HLH
HH L
HHH
H = HIGH Logic Level, L = LOW Logic Level
X = Irrelevant, Z = High Impedance (off)
D0, D1. . . D7 = The level of the respective D input
Logic Diagram
Strobe
S
H
L
L
L
L
L
L
L
L
Outputs
YW
ZZ
D0 D0
D1 D1
D2 D2
D3 D3
D4 D4
D5 D5
D6 D6
D7 D7
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