MM74HC259 Line Decoder Datasheet

MM74HC259 Datasheet, PDF, Equivalent


Part Number

MM74HC259

Description

8-Bit Addressable Latch/3-to-8 Line Decoder

Manufacture

Fairchild

Total Page 7 Pages
Datasheet
Download MM74HC259 Datasheet


MM74HC259
September 1983
Revised February 1999
MM74HC259
8-Bit Addressable Latch/3-to-8 Line Decoder
General Description
The MM74HC259 device utilizes advanced silicon-gate
CMOS technology to implement an 8-bit addressable latch,
designed for general purpose storage applications in digital
systems.
The MM74HC259 has a single data input (D), 8 latch out-
puts (Q1–Q8), 3 address inputs (A, B, and C), a common
enable input (G), and a common CLEAR input. To operate
this device as an addressable latch, data is held on the D
input, and the address of the latch into which the data is to
be entered is held on the A, B, and C inputs. When
ENABLE is taken LOW the data flows through to the
addressed output. The data is stored when ENABLE transi-
tions from LOW-to-HIGH. All unaddressed latches will
remain unaffected. With enable in the HIGH state the
device is deselected, and all latches remain in their previ-
ous state, unaffected by changes on the data or address
inputs. To eliminate the possibility of entering erroneous
data into the latches, the enable should be held HIGH
(inactive) while the address lines are changing.
If enable is held HIGH and CLEAR is taken LOW all eight
latches are cleared to a LOW state. If enable is LOW all
latches except the addressed latch will be cleared. The
addressed latch will instead follow the D input, effectively
implementing a 3-to-8 line decoder.
All inputs are protected from damage due to static dis-
charge by diodes to VCC and ground.
Features
s Typical propagation delay: 18 ns
s Wide supply range: 2–6V
s Low input current: 1 µA maximum
s Low quiescent current: 80 µA maximum (74HC Series)
Ordering Code:
Order Number Package Number Package Description
MM74HC259M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
MM74HC259SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC259MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC259N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Latch Selection Table
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
Select Inputs
CBA
LLL
L LH
LHL
L HH
HL L
HLH
HH L
HHH
H = HIGH level, L = LOW level
D = the level at the data input
Qi0 the level of Qi (i = 0, 1 .. .7, as appropriate)
before the indicated steady-state input
conditions were established.
Latch
Addressed
0
1
2
3
4
5
6
7
© 1999 Fairchild Semiconductor Corporation DS005006.prf
www.fairchildsemi.com

MM74HC259
Truth Table
Inputs
Clear
H
H
L
L
G
L
H
L
H
Outputs of
Addressed
Latch
D
Qi0
D
L
Each
Other
Output
Qi0
Qi0
L
L
Function
Addressable Latch
Memory
8-Line Decoder
Clear
Logic Diagram
www.fairchildsemi.com
2


Features MM74HC259 8-Bit Addressable Latch/3-to-8 Line Decoder September 1983 Revised F ebruary 1999 MM74HC259 8-Bit Addressab le Latch/3-to-8 Line Decoder General De scription The MM74HC259 device utilizes advanced silicon-gate CMOS technology to implement an 8-bit addressable latch , designed for general purpose storage applications in digital systems. The MM 74HC259 has a single data input (D), 8 latch outputs (Q1–Q8), 3 address inpu ts (A, B, and C), a common enable input (G), and a common CLEAR input. To oper ate this device as an addressable latch , data is held on the D input, and the address of the latch into which the dat a is to be entered is held on the A, B, and C inputs. When ENABLE is taken LOW the data flows through to the addresse d output. The data is stored when ENABL E transitions from LOW-to-HIGH. All una ddressed latches will remain unaffected . With enable in the HIGH state the dev ice is deselected, and all latches rema in in their previous state, unaffected by changes on the data or .
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