with Clear. MM74HC273 Datasheet


MM74HC273 Clear. Datasheet pdf. Equivalent


Part Number

MM74HC273

Description

Octal D-Type Flip-Flops with Clear

Manufacture

Fairchild

Total Page 7 Pages
Datasheet
Download MM74HC273 Datasheet


MM74HC273
September 1983
Revised February 1999
MM74HC273
Octal D-Type Flip-Flops with Clear
General Description
The MM74HC273 edge triggered flip-flops utilize advanced
silicon-gate CMOS technology to implement D-type flip-
flops. They possess high noise immunity, low power, and
speeds comparable to low power Schottky TTL circuits.
This device contains 8 master-slave flip-flops with a com-
mon clock and common clear. Data on the D input having
the specified setup and hold times is transferred to the Q
output on the LOW-to-HIGH transition of the CLOCK input.
The CLEAR input when LOW, sets all outputs to a low
state.
Each output can drive 10 low power Schottky TTL equiva-
lent loads. The MM74HC273 is functionally as well as pin
compatible to the 74LS273. All inputs are protected from
damage due to static discharge by diodes to VCC and
ground.
Features
s Typical propagation delay: 18 ns
s Wide operating voltage range
s Low input current: 1 µA maximum
s Low quiescent current: 80 µA (74 Series)
s Output drive: 10 LS-TTL loads
Ordering Code:
Order Number Package Number
Package Description
MM74HC273M
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-153, 0.300” Wide
MM74HC273SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC273MTC
MTC20
20-Lead thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC273N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
© 1999 Fairchild Semiconductor Corporation DS005331.prf
www.fairchildsemi.com

MM74HC273
Truth Table
Clear
L
H
H
H
(Each Flip-Flop)
Inputs
Clock
D
XX
H
L
LX
Outputs
Q
L
H
L
Q0
H = HIGH Level (Steady State)
L = LOW Level (Steady State)
X = Don’t Care
↑ = Transition from LOW-to-HIGH level
Q0 = The level of Q before the indicated steady state input conditions were
established
Logic Diagram
www.fairchildsemi.com
2


Features MM74HC273 Octal D-Type Flip-Flops with C lear September 1983 Revised February 1 999 MM74HC273 Octal D-Type Flip-Flops with Clear General Description The MM74 HC273 edge triggered flip-flops utilize advanced silicon-gate CMOS technology to implement D-type flipflops. They pos sess high noise immunity, low power, an d speeds comparable to low power Schott ky TTL circuits. This device contains 8 master-slave flip-flops with a common clock and common clear. Data on the D i nput having the specified setup and hol d times is transferred to the Q output on the LOW-to-HIGH transition of the CL OCK input. The CLEAR input when LOW, se ts all outputs to a low state. Each out put can drive 10 low power Schottky TTL equivalent loads. The MM74HC273 is fun ctionally as well as pin compatible to the 74LS273. All inputs are protected f rom damage due to static discharge by d iodes to VCC and ground. Features s Ty pical propagation delay: 18 ns s Wide o perating voltage range s Low input current: 1 µA maximum s Low .
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