Binary Counter. MM74HC4020 Datasheet


MM74HC4020 Counter. Datasheet pdf. Equivalent


Part Number

MM74HC4020

Description

14-Stage Binary Counter 12-Stage Binary Counter

Manufacture

Fairchild

Total Page 8 Pages
Datasheet
Download MM74HC4020 Datasheet


MM74HC4020
February 1984
Revised February 1999
MM74HC4020 • MM74HC4040
14-Stage Binary Counter • 12-Stage Binary Counter
General Description
The MM74HC4020, MM74HC4040, are high speed binary
ripple carry counters. These counters are implemented uti-
lizing advanced silicon-gate CMOS technology to achieve
speed performance similar to LS-TTL logic while retaining
the low power and high noise immunity of CMOS.
The MM74HC4020 is a 14 stage counter and the
MM74HC4040 is a 12-stage counter. Both devices are
incremented on the falling edge (negative transition) of the
input clock, and all their outputs are reset to a low level by
applying a logical high on their reset input.
These devices are pin equivalent to the CD4020 and
CD4040 respectively. All inputs are protected from damage
due to static discharge by protection diodes to VCC and
ground.
Features
s Typical propagation delay: 16 ns
s Wide operating voltage range: 2–6V
s Low input current: 1 µA maximum
s Low quiescent current: 80 µA maximum (74HC Series)
s Output drive capability: 10 LS-TTL loads
Ordering Code:
Order Number Package Number
Package Description
MM74HC4020M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74HC4020SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC4020MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC4020N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
MM74HC4040M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74HC4040SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC4040MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC4040N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignments for DIP, SOIC, SOP and TSSOP
MM74HC4020
© 1999 Fairchild Semiconductor Corporation DS005216.prf
MM74HC4040
www.fairchildsemi.com

MM74HC4020
Logic Diagrams
MM74HC4020
MM74HC4040
www.fairchildsemi.com
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Features MM74HC4020 • MM74HC4040 14-Stage Binar y Counter • 12-Stage Binary Counter February 1984 Revised February 1999 MM 74HC4020 • MM74HC4040 14-Stage Binary Counter • 12-Stage Binary Counter Ge neral Description The MM74HC4020, MM74H C4040, are high speed binary ripple car ry counters. These counters are impleme nted utilizing advanced silicon-gate CM OS technology to achieve speed performa nce similar to LS-TTL logic while retai ning the low power and high noise immun ity of CMOS. The MM74HC4020 is a 14 sta ge counter and the MM74HC4040 is a 12-s tage counter. Both devices are incremen ted on the falling edge (negative trans ition) of the input clock, and all thei r outputs are reset to a low level by a pplying a logical high on their reset i nput. These devices are pin equivalent to the CD4020 and CD4040 respectively. All inputs are protected from damage du e to static discharge by protection dio des to VCC and ground. Features s Typi cal propagation delay: 16 ns s Wide operating voltage range: 2–6V s Low.
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