MM74HC4046 Lock Loop Datasheet

MM74HC4046 Datasheet, PDF, Equivalent


Part Number

MM74HC4046

Description

CMOS Phase Lock Loop

Manufacture

Fairchild

Total Page 16 Pages
Datasheet
Download MM74HC4046 Datasheet


MM74HC4046
February 1984
Revised February 1999
MM74HC4046
CMOS Phase Lock Loop
General Description
The MM74HC4046 is a low power phase lock loop utilizing
advanced silicon-gate CMOS technology to obtain high fre-
quency operation both in the phase comparator and VCO
sections. This device contains a low power linear voltage
controlled oscillator (VCO), a source follower, and three
phase comparators. The three phase comparators have a
common signal input and a common comparator input. The
signal input has a self biasing amplifier allowing signals to
be either capacitively coupled to the phase comparators
with a small signal or directly coupled with standard input
logic levels. This device is similar to the CD4046 except
that the Zener diode of the metal gate CMOS device has
been replaced with a third phase comparator.
Phase Comparator I is an exclusive OR (XOR) gate. It pro-
vides a digital error signal that maintains a 90 phase shift
between the VCO’s center frequency and the input signal
(50% duty cycle input waveforms). This phase detector is
more susceptible to locking onto harmonics of the input fre-
quency than phase comparator I, but provides better noise
rejection.
Phase comparator III is an SR flip-flop gate. It can be used
to provide the phase comparator functions and is similar to
the first comparator in performance.
Phase comparator II is an edge sensitive digital sequential
network. Two signal outputs are provided, a comparator
output and a phase pulse output. The comparator output is
a 3-STATE output that provides a signal that locks the VCO
output signal to the input signal with 0 phase shift between
them. This comparator is more susceptible to noise throw-
ing the loop out of lock, but is less likely to lock onto har-
monics than the other two comparators.
In a typical application any one of the three comparators
feed an external filter network which in turn feeds the VCO
input. This input is a very high impedance CMOS input
which also drives the source follower. The VCO’s operating
frequency is set by three external components connected
to the C1A, C1B, R1 and R2 pins. An inhibit pin is provided
to disable the VCO and the source follower, providing a
method of putting the IC in a low power state.
The source follower is a MOS transistor whose gate is con-
nected to the VCO input and whose drain connects the
Demodulator output. This output normally is used by tying
a resistor from pin 10 to ground, and provides a means of
looking at the VCO input without loading down modifying
the characteristics of the PLL filter.
Features
s Low dynamic power consumption: (VCC = 4.5V)
s Maximum VCO operating frequency:
12 MHz (VCC = 4.5V)
s Fast comparator response time (VCC = 4.5V)
Comparator I: 25 ns
Comparator II: 30 ns
Comparator III: 25 ns
s VCO has high linearity and high temperature stability
Ordering Code:
Order Number Package Number
Package Description
MM74HC4046M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74HC4046SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC4046MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC4046N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 1999 Fairchild Semiconductor Corporation DS005352.prf
www.fairchildsemi.com

MM74HC4046
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Block Diagram
www.fairchildsemi.com
2


Features MM74HC4046 CMOS Phase Lock Loop Februar y 1984 Revised February 1999 MM74HC404 6 CMOS Phase Lock Loop General Descript ion The MM74HC4046 is a low power phase lock loop utilizing advanced silicon-g ate CMOS technology to obtain high freq uency operation both in the phase compa rator and VCO sections. This device con tains a low power linear voltage contro lled oscillator (VCO), a source followe r, and three phase comparators. The thr ee phase comparators have a common sign al input and a common comparator input. The signal input has a self biasing am plifier allowing signals to be either c apacitively coupled to the phase compar ators with a small signal or directly c oupled with standard input logic levels . This device is similar to the CD4046 except that the Zener diode of the meta l gate CMOS device has been replaced wi th a third phase comparator. Phase Comp arator I is an exclusive OR (XOR) gate. It provides a digital error signal tha t maintains a 90 phase shift between the VCO’s center frequency.
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