MM74HC4050 Down Converter Datasheet

MM74HC4050 Datasheet, PDF, Equivalent


Part Number

MM74HC4050

Description

Hex Logic Level Down Converter

Manufacture

Fairchild

Total Page 6 Pages
Datasheet
Download MM74HC4050 Datasheet


MM74HC4050
February 1984
Revised October 1999
MM74HC4049 • MM74HC4050
Hex Inverting Logic Level Down Converter •
Hex Logic Level Down Converter
General Description
The MM74HC4049 and the MM74HC4050 utilize
advanced silicon-gate CMOS technology, and have a mod-
ified input protection structure that enables these parts to
be used as logic level translators which will convert high
level logic to a low level logic while operating from the low
logic supply. For example, 0–15V CMOS logic can be con-
verted to 0–5V logic when using a 5V supply. The modified
input protection has no diode connected to VCC, thus allow-
ing the input voltage to exceed the supply. The lower zener
diode protects the input from both positive and negative
static voltages. In addition each part can be used as a sim-
ple buffer or inverter without level translation. The
MM74HC4049 is pin and functionally compatible to the
CD4049BC and the MM74HC4050 is compatible to the
CD4050BC
Features
s Typical propagation delay: 8 ns
s Wide power supply range: 2V–6V
s Low quiescent supply current: 20 µA maximum (74HC)
s Fanout of 10 LS-TTL loads
Ordering Code:
Order Number Package Number Package Description
MM74HC4049M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74HC4049SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC4049MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153. 4.4mm Wide
MM74HC4049N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
MM74HC4050M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74HC4050SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC4050MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153. 4.4mm Wide
MM74HC4050N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
MM74HC4049
© 1999 Fairchild Semiconductor Corporation DS005214
MM74HC4050
www.fairchildsemi.com

MM74HC4050
Absolute Maximum Ratings(Note 1)
(Note 2)
Supply Voltage (VCC)
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (IZK, IOK)
DC Output Current, per pin (IOUT)
DC VCC or GND Current, per pin (ICC)
Storage Temperature Range (TSTG)
Power Dissipation (PD)
(Note 3)
S.O. Package only
Lead Temperature (TL)
(Soldering 10 seconds)
0.5 to +7.0V
1.5 to +18V
0.5 to VCC +0.5V
20 mA
±25 mA
±50 mA
65°C to +150°C
600 mW
500 mW
260°C
Recommended Operating
Conditions
Min Max Units
Supply Voltage (VCC)
DC Input Voltage
26
0 15
V
V
(VIN)
DC Output Voltage
(VOUT)
Operating Temperature Range (TA)
Input Rise or Fall Times
0 VCC
40 +85
V
°C
(tr, tf) VCC = 2.0V
1000 ns
VCC = 4.5V
500 ns
VCC = 6.0V
400 ns
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating — plastic “N” package:
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
VCC
TA = 25°C
TA = −40°C to 85°C TA = −55°C to 125°C Units
Typ Guaranteed Limits
VIH Minimum HIGH Level Input
Voltage
2.0V
4.5V
1.5
3.15
1.5
3.15
1.5
3.15
V
V
6.0V
4.2 4.2
4.2 V
VIL Maximum LOW Level Input
Voltage
2.0V
4.5V
0.5
1.35
0.5
1.35
0.5
1.35
V
V
6.0V
1.8 1.8
1.8 V
VOH Minimum HIGH Level
Output Voltage
VIN = VIH or VIL
|IOUT| 20 µA
2.0V
4.5V
2.0
4.5
1.9
4.4
1.9
4.4
1.9 V
4.4 V
6.0V
6.0
5.9
5.9
5.9 V
VOL Maximum LOW Level
Output Voltage
VIN = VIH or VIL
|IOUT| 4.0 mA
|IOUT| 5.2 mA
VIN = VIH or VIL
|IOUT| 20 µA
4.5V
6.0V
2.0V
4.5V
4.2
5.7
0
0
3.98
5.48
0.1
0.1
3.84
5.34
0.1
0.1
3.7 V
5.2 V
0.1 V
0.1 V
6.0V
0
0.1
0.1
0.1 V
VIN = VIH or VIL
|IOUT| 4 mA
4.5V
0.2
0.26
0.33
0.4 V
|IOUT| 5.2 mA
6.0V
0.2
0.26
0.33
0.4 V
IIN
Maximum Input Current
VIN = VCC or GND
6.0V
±0.1
±1.0
±1.0
µA
VIN = 15V
2.0V
±0.5
±5
±5 µA
ICC
Maximum Quiescent Supply VIN = VCC or GND
6.0V
2.0 20
40 µA
Current
IOUT = 0 µA
Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage cur-
rent (IIN, ICC, IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
www.fairchildsemi.com
2


Features MM74HC4049 • MM74HC4050 Hex Inverting Logic Level Down Converter • Hex Logi c Level Down Converter February 1984 R evised October 1999 MM74HC4049 • MM7 4HC4050 Hex Inverting Logic Level Down Converter • Hex Logic Level Down Conv erter General Description The MM74HC404 9 and the MM74HC4050 utilize advanced s ilicon-gate CMOS technology, and have a modified input protection structure th at enables these parts to be used as lo gic level translators which will conver t high level logic to a low level logic while operating from the low logic sup ply. For example, 0–15V CMOS logic ca n be converted to 0–5V logic when usi ng a 5V supply. The modified input prot ection has no diode connected to VCC, t hus allowing the input voltage to excee d the supply. The lower zener diode pro tects the input from both positive and negative static voltages. In addition e ach part can be used as a simple buffer or inverter without level translation. The MM74HC4049 is pin and functionally compatible to the CD4049BC and the .
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