MM74HC4514

MM74HC4514 4-to-16 Line Decoder with Latch February 1984 Revised February 2000 MM74HC4514 4-to-16 Line Decoder with Latch General Description The MM74HC4514 utilizes advanced silicon-gate CMOS technology, which is well suited to memory address decoding or data routing application. It possesses high noise immunity and low power dissipation usually associated with CMOS circuitry, yet speeds comparable to low power Schottky TTL circuits. It can drive up to 10 LS-TTL loads. The MM74HC4514 contain a 4-to-16 line decoder and a 4bit latch. The latch can store the data on the select inputs, thus allowing a selected output to remain HIGH even though the select data has changed. When the LATCH ENABLE input to the latches is HIGH the outputs will change with the inputs. When LATCH ENABLE goes LOW the data on the select inputs is stored in the latches. The four select inputs determine which output will go HIGH provided the INHIBIT input is LOW. If the INHIBIT input is HIGH all outputs are held LOW thus disabling the decoder. The MM74HC4514 is functionally and pinout equivalent to the CD4514BC and the MC1451BC. All inputs are protected against damage due to static discharge diodes from VCC and ground. Features s Typical propagation delay: 18 ns s Low quiescent power: 80 µA maximum (74HC Series) s Low input current: 1 µA maximum s Fanout of 10 LS-TTL loads (74HC Series) Ordering Code: Order Number MM74HC4514WM MM74HC4514MTC MM74HC4514N Package Number M24B MTC24 N24C Package Description...