MM74HC4514 with Latch Datasheet

MM74HC4514 Datasheet, PDF, Equivalent


Part Number

MM74HC4514

Description

4-to-16 Line Decoder with Latch

Manufacture

Fairchild

Total Page 7 Pages
Datasheet
Download MM74HC4514 Datasheet


MM74HC4514
February 1984
Revised February 2000
MM74HC4514
4-to-16 Line Decoder with Latch
General Description
The MM74HC4514 utilizes advanced silicon-gate CMOS
technology, which is well suited to memory address decod-
ing or data routing application. It possesses high noise
immunity and low power dissipation usually associated with
CMOS circuitry, yet speeds comparable to low power
Schottky TTL circuits. It can drive up to 10 LS-TTL loads.
The MM74HC4514 contain a 4-to-16 line decoder and a 4-
bit latch. The latch can store the data on the select inputs,
thus allowing a selected output to remain HIGH even
though the select data has changed. When the LATCH
ENABLE input to the latches is HIGH the outputs will
change with the inputs. When LATCH ENABLE goes LOW
the data on the select inputs is stored in the latches. The
four select inputs determine which output will go HIGH pro-
vided the INHIBIT input is LOW. If the INHIBIT input is
HIGH all outputs are held LOW thus disabling the decoder.
The MM74HC4514 is functionally and pinout equivalent to
the CD4514BC and the MC1451BC. All inputs are pro-
tected against damage due to static discharge diodes from
VCC and ground.
Features
s Typical propagation delay: 18 ns
s Low quiescent power: 80 µA maximum (74HC Series)
s Low input current: 1 µA maximum
s Fanout of 10 LS-TTL loads (74HC Series)
Ordering Code:
Order Number Package Number
Package Description
MM74HC4514WM
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-0013, 0.300” Wide
MM74HC4514MTC
MTC24
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC4514N
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2000 Fairchild Semiconductor Corporation DS005215
www.fairchildsemi.com

MM74HC4514
Connection Diagram
Top View
Logic Diagram
Truth Table
LE Inhibit
HL
HL
HL
HL
HL
HL
HL
HL
HL
HL
HL
HL
HL
HL
HL
HL
XH
LL
Data Inputs
D C B A Selected
Output
High
LLLL
S0
L L LH
S1
L LHL
S2
L LHH
S3
LHL L
S4
LHLH
S5
L HH L
S6
L HHH
S7
HL L L
S8
HLLH
S9
HLHL
S10
H LHH
S11
HHL L
S12
HH L H
S13
HHHL
S14
HHHH
S15
All
X X X X Outputs = 0
Latched
XXXX
Data
www.fairchildsemi.com
2


Features MM74HC4514 4-to-16 Line Decoder with Lat ch February 1984 Revised February 2000 MM74HC4514 4-to-16 Line Decoder with Latch General Description The MM74HC451 4 utilizes advanced silicon-gate CMOS t echnology, which is well suited to memo ry address decoding or data routing app lication. It possesses high noise immun ity and low power dissipation usually a ssociated with CMOS circuitry, yet spee ds comparable to low power Schottky TTL circuits. It can drive up to 10 LS-TTL loads. The MM74HC4514 contain a 4-to-1 6 line decoder and a 4bit latch. The la tch can store the data on the select in puts, thus allowing a selected output t o remain HIGH even though the select da ta has changed. When the LATCH ENABLE i nput to the latches is HIGH the outputs will change with the inputs. When LATC H ENABLE goes LOW the data on the selec t inputs is stored in the latches. The four select inputs determine which outp ut will go HIGH provided the INHIBIT in put is LOW. If the INHIBIT input is HIGH all outputs are held L.
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