MM74HC540 3-STATE Buffer Datasheet

MM74HC540 Datasheet, PDF, Equivalent


Part Number

MM74HC540

Description

Inverting Octal 3-STATE Buffer

Manufacture

Fairchild

Total Page 6 Pages
Datasheet
Download MM74HC540 Datasheet


MM74HC540
September 1983
Revised February 1999
MM74HC540 • MM74HC541
Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer
General Description
The MM74HC540 and MM74HC541 3-STATE buffers uti-
lize advanced silicon-gate CMOS technology. They pos-
sess high drive current outputs which enable high speed
operation even when driving large bus capacitances.
These circuits achieve speeds comparable to low power
Schottky devices, while retaining the advantage of CMOS
circuitry, i.e., high noise immunity, and low power consump-
tion. Both devices have a fanout of 15 LS-TTL equivalent
inputs.
The MM74HC540 is an inverting buffer and the
MM74HC541 is a non-inverting buffer. The 3-STATE con-
trol gate operates as a two-input NOR such that if either G1
or G2 are HIGH, all eight outputs are in the high-imped-
ance state.
In order to enhance PC board layout, the MM74HC540 and
MM74HC541 offers a pinout having inputs and outputs on
opposite sides of the package. All inputs are protected from
damage due to static discharge by diodes to VCC and
ground.
Features
s Typical propagation delay: 12 ns
s 3-STATE outputs for connection to system buses
s Wide power supply range: 2–6V
s Low quiescent current: 80 µA maximum (74HC Series)
s Output current: 6 mA
Ordering Code:
Order Number Package Number
Package Description
MM74HC540WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74HC540SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC540MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC540N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
MM74HC541WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74HC541SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC541MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC541N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
MM74HC540
© 1999 Fairchild Semiconductor Corporation DS005341.prf
Top View
MM74HC541
www.fairchildsemi.com

MM74HC540
Absolute Maximum Ratings(Note 1)
(Note 2)
Supply Voltage (VCC)
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (ICD)
DC Output Current, per pin (IOUT)
DC VCC or GND Current,
per pin (ICC)
Storage Temperature Range (TSTG)
Power Dissipation (PD)
(Note 3)
S.O. Package only
Lead Temperature (TL)
(Soldering 10 seconds)
0.5 to +7.0V
1.5 to VCC +1.5V
0.5 to VCC +0.5V
±20 mA
±35 mA
±70 mA
65°C to +150°C
600 mW
500 mW
260°C
Recommended Operating
Conditions
Min Max Units
Supply Voltage (VCC)
DC Input or Output Voltage
26V
(VIN, VOUT)
Operating Temperature Range (TA)
Input Rise or Fall Times
0
40
VCC
+85
V
°C
(tr, tf) VCC = 2.0V
1000 ns
VCC = 4.5V
500 ns
VCC = 6.0V
400 ns
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating — plastic “N” package:
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
VCC
TA = 25°C
TA = −40 to 85°C TA = −55 to 125°C
Units
Typ Guaranteed Limits
VIH Minimum HIGH Level
Input Voltage
2.0V
4.5V
1.5
3.15
1.5
3.15
1.5
3.15
V
V
6.0V
4.2 4.2
4.2 V
VIL Maximum LOW Level
Input Voltage
2.0V
4.5V
0.5
1.35
0.5
1.35
0.5
1.35
V
V
6.0V
1.8 1.8
1.8 V
VOH Minimum HIGH Level
Output Voltage
VIN = VIH or VIL
|IOUT| 20 µA
2.0V
4.5V
2.0
4.5
1.9
4.4
1.9
4.4
1.9 V
4.4 V
6.0V
6.0
5.9
5.9
5.9 V
VOL Maximum LOW Level
Output Voltage
VIN = VIH or VIL
|IOUT| 6.0 mA
|IOUT| 7.8 mA
VIN = VIH or VIL
|IOUT| 20 µA
4.5V
6.0V
2.0V
4.5V
4.2
5.7
0
0
3.98
5.48
0.1
0.1
3.84
5.34
0.1
0.1
3.7 V
5.2 V
0.1 V
0.1 V
6.0V
0
0.1
0.1
0.1 V
IIN Maximum Input
Current
VIN = VIH or VIL
|IOUT| 6.0 mA
|IOUT| 7.8 mA
VIN = VCC or GND
4.5V
6.0V
6.0V
0.2
0.2
0.26
0.26
±0.1
0.33
0.33
±1.0
0.4
0.4
±1.0
V
V
µA
IOZ Maximum 3-STATE
Output Leakage
Current
VIN = VIH or VIL, G = VIH
VOUT = VCC or GND
6.0V
±0.5
±5
±10 µA
ICC Maximum Quiescent
VIN = VCC or GND
6.0V
8.0 80
160 µA
Supply Current
IOUT = 0 µA
Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage cur-
rent (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
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2


Features MM74HC540 • MM74HC541 Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer September 1983 Revised February 1999 MM74HC540 • MM74HC541 Inverting Octa l 3-STATE Buffer • Octal 3-STATE Buff er General Description The MM74HC540 an d MM74HC541 3-STATE buffers utilize adv anced silicon-gate CMOS technology. The y possess high drive current outputs wh ich enable high speed operation even wh en driving large bus capacitances. Thes e circuits achieve speeds comparable to low power Schottky devices, while reta ining the advantage of CMOS circuitry, i.e., high noise immunity, and low powe r consumption. Both devices have a fano ut of 15 LS-TTL equivalent inputs. The MM74HC540 is an inverting buffer and th e MM74HC541 is a non-inverting buffer. The 3-STATE control gate operates as a two-input NOR such that if either G1 or G2 are HIGH, all eight outputs are in the high-impedance state. In order to e nhance PC board layout, the MM74HC540 a nd MM74HC541 offers a pinout having inputs and outputs on opposite side.
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