MM74HC573 D-Type Latch Datasheet

MM74HC573 Datasheet, PDF, Equivalent


Part Number

MM74HC573

Description

3-STATE Octal D-Type Latch

Manufacture

Fairchild

Total Page 8 Pages
Datasheet
Download MM74HC573 Datasheet


MM74HC573
September 1983
Revised May 2000
MM74HC573
3-STATE Octal D-Type Latch
General Description
The MM74HC573 high speed octal D-type latches utilize
advanced silicon-gate P-well CMOS technology. They pos-
sess the high noise immunity and low power consumption
of standard CMOS integrated circuits, as well as the ability
to drive 15 LS-TTL loads. Due to the large output drive
capability and the 3-STATE feature, these devices are ide-
ally suited for interfacing with bus lines in a bus organized
system.
When the LATCH ENABLE(LE) input is HIGH, the Q out-
puts will follow the D inputs. When the LATCH ENABLE
goes LOW, data at the D inputs will be retained at the out-
puts until LATCH ENABLE returns HIGH again. When a
HIGH logic level is applied to the OUTPUT CONTROL OC
input, all outputs go to a HIGH impedance state, regardless
of what signals are present at the other inputs and the state
of the storage elements.
The 74HC logic family is speed, function and pinout com-
patible with the standard 74LS logic family. All inputs are
protected from damage due to static discharge by internal
diode clamps to VCC and ground.
Features
s Typical propagation delay: 18 ns
s Wide operating voltage range: 2 to 6 volts
s Low input current: 1 µA maximum
s Low quiescent current: 80 µA maximum (74HC Series)
s Compatible with bus-oriented systems
s Output drive capability: 15 LS-TTL loads
Ordering Code:
Order Number Package Number
Package Description
MM74HC573WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
MM74HC573SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC573MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC573N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Truth Table
Output
Latch
Data
Output
Control
Enable
L HHH
LHL L
L L X Q0
HX X Z
H = HIGH Level
L = LOW Level
Q0 = Level of output before steady-state input conditions were established.
Z = High Impedance
X = Don't Care
Top View
© 2000 Fairchild Semiconductor Corporation DS005212
www.fairchildsemi.com

MM74HC573
Absolute Maximum Ratings(Note 1)
(Note 2)
Supply Voltage (VCC)
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (IIK, IOK)
DC Output Current, per pin (IOUT)
DC VCC or GND Current, per pin (ICC)
Storage Temperature Range (TSTG)
Power Dissipation (PD)
(Note 3)
S.O. Package only
Lead Temperature (TL)
(Soldering 10 seconds)
0.5 to +7.0V
1.5 to VCC +1.5V
0.5 to VCC +0.5V
±20 mA
±35 mA
±70 mA
65°C to +150°C
600 mW
500 mW
260°C
Recommended Operating
Conditions
Min Max Units
Supply Voltage (VCC)
DC Input or Output Voltage
(VIN, VOUT)
Operating Temperature Range (TA)
Input Rise or Fall Times
26
0 VCC
40 +85
V
V
°C
(tr, tf) VCC = 2.0V
1000 ns
VCC = 4.5V
500 ns
VCC = 6.0V
400 ns
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating plastic Npackage:
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
VCC
TA = 25°C
TA = −40 to 85°C TA = −55 to 125°C
Units
Typ Guaranteed Limits
VIH Minimum HIGH Level Input
Voltage
2.0V
4.5V
1.5
3.15
1.5
3.15
1.5
3.15
V
V
6.0V
4.2 4.2
4.2 V
VIL Maximum LOW Level Input
Voltage
2.0V
4.5V
0.5
1.35
0.5
1.35
0.5
1.35
V
V
6.0V
1.8 1.8
1.8 V
VOH Minimum HIGH Level Output VIN = VIH or VIL
Voltage
|IOUT| 20 µA
2.0V
4.5V
2.0
4.5
1.9
4.4
1.9
4.4
1.9 V
4.4 V
6.0V
6.0
5.9
5.9
5.9 V
VIN = VIH or VIL
|IOUT| 6.0 mA
|IOUT| 7.8 mA
VOL Maximum LOW Level Output VIN = VIH or VIL
Voltage
|IOUT| 20 µA
4.5V 4.2 3.98
6.0V 5.7 5.48
2.0V
4.5V
0
0
0.1
0.1
3.84
5.34
0.1
0.1
3.7 V
5.2 V
0.1 V
0.1 V
6.0V
0
0.1
0.1
0.1 V
IIN
IOZ
ICC
ICC
Maximum Input Current
Maximum 3-STATE Output
Leakage Current
Maximum Quiescent Supply
Current
Quiescent Supply Current
per Input Pin
VIN = VIH or VIL
|IOUT| 6.0 mA
|IOUT| 7.8 mA
VIN = VCC or GND
VOUT = VCC or GND
OC = VIH
VIN = VCC or GND
IOUT = 0 µA
VCC = 5.5V
VIN = 2.4V
or 0.4V (Note 4)
4.5V
6.0V
6.0V
6.0V
6.0V
OE
LE
DATA
0.2
0.2
1.0
0.6
0.4
0.26
0.26
±0.1
±0.5
8.0
1.5
0.8
0.5
0.33
0.33
±1.0
±5.0
80
1.8
1.0
0.6
0.4
0.4
±1.0
±10
160
2.0
1.1
0.7
V
V
µA
µA
µA
mA
mA
mA
Note 4: For a power supply of 5V ±10% the worst-case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst-case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst-case leakage cur-
rent (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
www.fairchildsemi.com
2


Features MM74HC573 3-STATE Octal D-Type Latch Se ptember 1983 Revised May 2000 MM74HC57 3 3-STATE Octal D-Type Latch General De scription The MM74HC573 high speed octa l D-type latches utilize advanced silic on-gate P-well CMOS technology. They po ssess the high noise immunity and low p ower consumption of standard CMOS integ rated circuits, as well as the ability to drive 15 LS-TTL loads. Due to the la rge output drive capability and the 3-S TATE feature, these devices are ideally suited for interfacing with bus lines in a bus organized system. When the LAT CH ENABLE(LE) input is HIGH, the Q outp uts will follow the D inputs. When the LATCH ENABLE goes LOW, data at the D in puts will be retained at the outputs un til LATCH ENABLE returns HIGH again. Wh en a HIGH logic level is applied to the OUTPUT CONTROL OC input, all outputs g o to a HIGH impedance state, regardless of what signals are present at the oth er inputs and the state of the storage elements. The 74HC logic family is speed, function and pinout c.
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