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MM74HC597 Dataheets PDF



Part Number MM74HC597
Manufacturers Fairchild
Logo Fairchild
Description 8-Bit Shift Registers with Input Latches
Datasheet MM74HC597 DatasheetMM74HC597 Datasheet (PDF)

MM74HC597 8-Bit Shift Registers with Input Latches January 1988 Revised August 2000 MM74HC597 8-Bit Shift Registers with Input Latches General Description This high speed register utilizes advanced silicon-gate CMOS technology. It has the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 10 LS-TTL loads. The MM74HC597 comes in a 16-pin package and consists of an 8-bit storage latch feeding a parallel-in, serial-out 8-bit shift r.

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MM74HC597 8-Bit Shift Registers with Input Latches January 1988 Revised August 2000 MM74HC597 8-Bit Shift Registers with Input Latches General Description This high speed register utilizes advanced silicon-gate CMOS technology. It has the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 10 LS-TTL loads. The MM74HC597 comes in a 16-pin package and consists of an 8-bit storage latch feeding a parallel-in, serial-out 8-bit shift register. Both the storage register and shift register have positive-edge triggered clocks. the shift register also has direct load (from storage) and clear inputs. The 74HC logic family is speed, function, and pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground. Features s 8-bit parallel storage register inputs s Wide operating voltage range: 2V–6V s Shift register has direct overriding load and clear s Guaranteed shift frequency: DC to 30 MHz s Low quiescent current: 80 µA maximum Ordering Code: Order Number MM74HC597M MM74HC597SJ MM74HC597N Package Number M16A M16D N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table RCK SCK SLOAD SCLR Function Data Loaded to input latches Data loaded from inputs to shift register Data transferred from X L H input latches to shift register Invalid logic, state of X X X X X L H H L L H shift register indeterminate when signals removed Shift register cleared Shift register clocked Qn = Qn−1, Q 0 = SER ↑ ↑ No clock edge X X X L X H ↑ Top View © 2000 Fairchild Semiconductor Corporation DS005343 www.fairchildsemi.com MM74HC597 Functional Block Diagram (Positive Logic) Timing Diagram www.fairchildsemi.com 2 MM74HC597 Absolute Maximum Ratings(Note 1) (Note 2) Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S.O. Package only Lead Temperature (TL) (Soldering 10 seconds) 260°C 600 mW 500 mW Recommended Operating Conditions Min Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) Operating Temperature Range (TA) Input Rise or Fall Times (tr, tf) VCC = 2.0V VCC = 4.5V VCC = 6.0V 1000 500 400 ns ns ns 0 VCC V 2 Max 6 Units V −0.5 to +7.0V −1.5 to VCC +1.5V −0.5 to VCC +0.5V ±20 mA ±25 mA ±70 mA −65°C to +150°C −40 +85 °C Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C. DC Electrical Characteristics Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage (Note 5) VOH Minimum HIGH Level Output Voltage VIN = VIH or VIL |IOUT| ≤ 20 µA Conditions (Note 4) VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0 4.5 6.0 4.2 5.2 0 0 0 0.2 0.2 TA = 25°C Typ 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 ±0.1 8.0 TA = −40 to 85°C TA = −55 to 125°C Guaranteed Limits 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 ±1.0 80 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 ±1.0 160 µA µA V V V V Units V VIN = VIH or VIL |IOUT| ≤ 4.0 mA |IOUT| ≤ 5.2 mA VOL Maximum LOW Level Output Voltage VIN = VIH or VIL |IOUT| ≤ 20 µA 2.0V 4.5V 6.0V VIN = VIH or VIL |IOUT| ≤ 4 mA |IOUT| ≤ 5.2 mA IIN ICC Maximum Input Current Maximum Quiescent Supply Current VIN = VCC or GND VIN = VCC or GND IOUT = 0 µA 4.5V 6.0V 6.0V 6.0V V 4.5V 6.0V Note 4: For a power supply of 5V ± 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. Note 5: VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY'89. 3 www.fairchildsemi.com MM74HC597 AC Electrical Characteristics Symbol fMAX tPHL tPLH tPHL tPLH tPHL tPLH tPHL tREM tS tS tS Parameter Maximum Operating Frequency of SCK Maximum Propagation Delay from SCK to QH Maximum Propagation Delay from SLOAD to QH Maximum propagation Delay from RCK to QH Maximum Propagation Delay from SCLR to QH Minimum Removal Time, SCLR to SCK Minimum Setup Time from RCK to SCK Minimum .


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