and Clear. MM74HC74A Datasheet


MM74HC74A Clear. Datasheet pdf. Equivalent


Part Number

MM74HC74A

Description

Dual D-Type Flip-Flop with Preset and Clear

Manufacture

Fairchild

Total Page 7 Pages
Datasheet
Download MM74HC74A Datasheet


MM74HC74A
September 1983
Revised February 1999
MM74HC74A
Dual D-Type Flip-Flop with Preset and Clear
General Description
The MM74HC74A utilizes advanced silicon-gate CMOS
technology to achieve operating speeds similar to the
equivalent LS-TTL part. It possesses the high noise immu-
nity and low power consumption of standard CMOS inte-
grated circuits, along with the ability to drive 10 LS-TTL
loads.
This flip-flop has independent data, preset, clear, and clock
inputs and Q and Q outputs. The logic level present at the
data input is transferred to the output during the positive-
going transition of the clock pulse. Preset and clear are
independent of the clock and accomplished by a low level
at the appropriate input.
The 74HC logic family is functionally and pinout compatible
with the standard 74LS logic family. All inputs are protected
from damage due to static discharge by internal diode
clamps to VCC and ground.
Features
s Typical propagation delay: 20 ns
s Wide power supply range: 2–6V
s Low quiescent current: 40 µA maximum (74HC Series)
s Low input current: 1 µA maximum
s Fanout of 10 LS-TTL loads
Ordering Code:
Order Number Package Number
Package Description
MM74HC74AM
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
MM74HC74ASJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC74AMTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC74AN
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Truth Table
Pin Assignments for DIP, SOIC, SOP and TSSOP
Inputs
Outputs
PR CLR CLK D
Q
Q
L H XX
H
L
HL
XX
L
H
L L X X H (Note 1) H (Note 1)
HH
H
H
L
HH
L
L
H
HH
LX
Q0
Q0
Note: Q0 = the level of Q before the indicated input conditions were estab-
lished.
Note 1: This configuration is nonstable; that is, it will not persist when pre-
set and clear inputs return to their inactive (HIGH) level.
© 1999 Fairchild Semiconductor Corporation DS005106.prf
www.fairchildsemi.com

MM74HC74A
Logic Diagram
www.fairchildsemi.com
2


Features MM74HC74A Dual D-Type Flip-Flop with Pre set and Clear September 1983 Revised F ebruary 1999 MM74HC74A Dual D-Type Fli p-Flop with Preset and Clear General De scription The MM74HC74A utilizes advanc ed silicon-gate CMOS technology to achi eve operating speeds similar to the equ ivalent LS-TTL part. It possesses the h igh noise immunity and low power consum ption of standard CMOS integrated circu its, along with the ability to drive 10 LS-TTL loads. This flip-flop has indep endent data, preset, clear, and clock i nputs and Q and Q outputs. The logic le vel present at the data input is transf erred to the output during the positive going transition of the clock pulse. Pr eset and clear are independent of the c lock and accomplished by a low level at the appropriate input. The 74HC logic family is functionally and pinout compa tible with the standard 74LS logic fami ly. All inputs are protected from damag e due to static discharge by internal d iode clamps to VCC and ground. Features s Typical propagation .
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