MM74HC76 and Clear Datasheet

MM74HC76 Datasheet, PDF, Equivalent


Part Number

MM74HC76

Description

Dual J-K Flip-Flops with Preset and Clear

Manufacture

National

Total Page 6 Pages
Datasheet
Download MM74HC76 Datasheet


MM74HC76
January 1988
MM54HC76 MM74HC76 Dual J-K Flip-Flops
with Preset and Clear
General Description
These high speed (30 MHz minimum) J-K Flip-Flops utilize
advanced silicon-gate CMOS technology to achieve the low
power consumption and high noise immunity of standard
CMOS integrated circuits along with the ability to drive 10
LS-TTL loads
Each flip-flop has independent J K PRESET CLEAR and
CLOCK inputs and Q and Q outputs These devices are
edge sensitive to the clock input and change state on the
negative going transition of the clock pulse Clear and pre-
set are independent of the clock and accomplished by a low
logic level on the corresponding input
The 54HC 74HC logic family is functionally as well as pin-
out compatible with the standard 54LS 74LS logic family
All inputs are protected from damage due to static dis-
charge by internal diode clamps to VCC and ground
Features
Y Typical propagation delay 16 ns
Y Wide operating voltage range
Y Low input current 1 mA maximum
Y Low quiescent current 40 mA maximum (74HC Series)
Y High output drive 10 LS-TTL loads
Connection and Logic Diagrams
Truth Table
Dual-In-Line Package
Inputs
Outputs
PR CLR CLK J L Q Q
LH
X XX H L
HL
X XX L H
LL
X XXL L
vH H
L L Q0 Q0
H H v HL H L
H H v LH L H
vH H
H H TOGGLE
HH
H X X Q0 Q0
This is an unstable condition and is not guaranteed
Top View
TL F 5074 – 1
Order Number MM54HC76 or MM74HC76
(1 of 2)
C1995 National Semiconductor Corporation TL F 5074
TL F 5074 – 2
TL F 5074 – 3
RRD-B30M105 Printed in U S A

MM74HC76
Absolute Maximum Ratings (Notes 1 2)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage (VCC)
b0 5 to a7 0V
DC Input Voltage (VIN)
b1 5 to VCCa1 5V
DC Output Voltage (VOUT)
b0 5 to VCCa0 5V
Clamp Diode Current (IIK IOK)
g20 mA
DC Output Current per pin (IOUT)
g25 mA
DC VCC or GND Current per pin (ICC)
g50 mA
Storage Temperature Range (TSTG)
b65 C to a150 C
Power Dissipation (PD)
(Note 3)
600 mW
S O Package only
500 mW
Lead Temp (TL) (Soldering 10 seconds)
260 C
Operating Conditions
Supply Voltage (VCC)
DC Input or Output Voltage
(VIN VOUT)
Operating Temp Range (TA)
MM74HC
MM54HC
Min
2
0
b40
b55
Input Rise or Fall Times
(tr tf)
VCCe2 0V
VCCe4 5V
VCCe6 0V
Max
6
VCC
a85
a125
1000
500
400
Units
V
V
C
C
ns
ns
ns
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
VCC
TAe25 C
Typ
74HC
54HC
TAeb40 to 85 C TAeb55 to 125 C
Guaranteed Limits
Units
VIH Minimum High Level
Input Voltage
2 0V
4 5V
6 0V
15 15
3 15 3 15
42 42
15 V
3 15 V
42 V
VIL Maximum Low Level
Input Voltage
2 0V
4 5V
6 0V
05 05
1 35 1 35
18 18
05 V
1 35 V
18 V
VOH
Minimum High Level VINeVIH or VIL
Output Voltage
lIOUTls20 mA
2 0V 2 0 1 9
4 5V 4 5 4 4
6 0V 6 0 5 9
19
44
59
19 V
44 V
59 V
VINeVIH or VIL
lIOUTls4 0 mA
lIOUTls5 2 mA
4 5V 4 2 3 98
6 0V 5 7 5 48
VOL Maximum Low Level VINeVIH or VIL
Output Voltage
lIOUTls20 mA
2 0V 0 0 1
4 5V 0 0 1
6 0V 0 0 1
3 84
5 34
01
01
01
37 V
52 V
01 V
01 V
01 V
VINeVIH or VIL
lIOUTls4 0 mA
lIOUTls5 2 mA
4 5V 0 2 0 26
6 0V 0 2 0 26
IIN Maximum Input VINeVCC or GND 6 0V
Current
g0 1
0 33
0 33
g1 0
04
04
g1 0
V
V
mA
ICC Maximum Quiescent VINeVCC or GND 6 0V 4 40
Supply Current
IOUTe0 mA
80 mA
Note 1 Absolute Maximum Ratings are those values beyond which damage to the device may occur
Note 2 Unless otherwise specified all voltages are referenced to ground
Note 3 Power Dissipation temperature derating plastic ‘‘N’’ package b12 mW C from 65 C to 85 C ceramic ‘‘J’’ package b12 mW C from 100 C to 125 C
Note 4 For a power supply of 5V g10% the worst case output voltages (VOH and VOL) occur for HC at 4 5V Thus the 4 5V values should be used when designing
with this supply Worst case VIH and VIL occur at VCCe5 5V and 4 5V respectively (The VIH value at 5 5V is 3 85V ) The worst case leakage current (IIN ICC and
IOZ) occur for CMOS at the higher voltage and so the 6 0V values should be used
VIL limits are currently tested at 20% of VCC The above VIL specification (30% of VCC) will be implemented no later than Q1 CY’89
2


Features MM54HC76 MM74HC76 Dual J-K Flip-Flops wi th Preset and Clear January 1988 MM54 HC76 MM74HC76 Dual J-K Flip-Flops with Preset and Clear General Description Th ese high speed (30 MHz minimum) J-K Fli p-Flops utilize advanced silicon-gate C MOS technology to achieve the low power consumption and high noise immunity of standard CMOS integrated circuits alon g with the ability to drive 10 LS-TTL l oads Each flip-flop has independent J K PRESET CLEAR and CLOCK inputs and Q an d Q outputs These devices are edge sens itive to the clock input and change sta te on the negative going transition of the clock pulse Clear and preset are in dependent of the clock and accomplished by a low logic level on the correspond ing input The 54HC 74HC logic family is functionally as well as pinout compati ble with the standard 54LS 74LS logic f amily All inputs are protected from dam age due to static discharge by internal diode clamps to VCC and ground Featur es Y Y Y Y Y Typical propagation delay 16 ns Wide operating vo.
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