MM74HCT244 3-STATE Buffer Datasheet

MM74HCT244 Datasheet, PDF, Equivalent


Part Number

MM74HCT244

Description

Inverting Octal 3-STATE Buffer Octal 3-STATE Buffer

Manufacture

Fairchild

Total Page 7 Pages
Datasheet
Download MM74HCT244 Datasheet


MM74HCT244
February 1984
Revised July 1999
MM74HCT240 • MM74HCT244
Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer
General Description
The MM74HCT240 and MM74HCT244 3-STATE buffers
utilize advanced silicon-gate CMOS technology and are
general purpose high speed inverting and non-inverting
buffers. They possess high drive current outputs which
enable high speed operation even when driving large bus
capacitances. These circuits achieve speeds comparable
to low power Schottky devices, while retaining the low
power consumption of CMOS. All three devices are TTL
input compatible and have a fanout of 15 LS-TTL equiva-
lent inputs.
MM74HCT devices are intended to interface between TTL
and NMOS components and standard CMOS devices.
These parts are also plug-in replacements for LS-TTL
devices and can be used to reduce power consumption in
existing designs.
The MM74HCT240 is an inverting buffer and the
MM74HCT244 is a non-inverting buffer. Each device has
two active low enables (1G and 2G), and each enable inde-
pendently controls 4 buffers.
All inputs are protected from damage due to static dis-
charge by diodes to VCC and Ground.
Features
s TTL input compatible
s Typical propagation delay: 14 ns
s 3-STATE outputs for connection to system buses
s Low quiescent current: 80 µA
s High output drive current: 6 mA (min)
Ordering Code:
Order Number Package Number
Package Description
MM74HCT240WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74HCT240SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HCT240MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HCT240N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
MM74HCT244WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74HCT244SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HCT244MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HCT244N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
MM74HCT240
© 1999 Fairchild Semiconductor Corporation DS005365
Top View
MM74HCT244
www.fairchildsemi.com

MM74HCT244
Truth Tables
MM74HCT240
1G 1A 1Y 2G 2A 2Y
L LHL LH
LHL LHL
HL ZHL Z
HHZHHZ
H = HIGH Level
L = LOW Level
Z = High Impedance
Logic Diagrams
MM74HCT240
MM74HCT244
1G 1A 1Y 2G 2A 2Y
LLLLLL
L HH L HH
HL ZHL Z
HHZHHZ
MM74HCT244
www.fairchildsemi.com
2


Features MM74HCT240 • MM74HCT244 Inverting Octa l 3-STATE Buffer • Octal 3-STATE Buff er February 1984 Revised July 1999 MM 74HCT240 • MM74HCT244 Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffe r General Description The MM74HCT240 an d MM74HCT244 3-STATE buffers utilize ad vanced silicon-gate CMOS technology and are general purpose high speed inverti ng and non-inverting buffers. They poss ess high drive current outputs which en able high speed operation even when dri ving large bus capacitances. These circ uits achieve speeds comparable to low p ower Schottky devices, while retaining the low power consumption of CMOS. All three devices are TTL input compatible and have a fanout of 15 LS-TTL equivale nt inputs. MM74HCT devices are intended to interface between TTL and NMOS comp onents and standard CMOS devices. These parts are also plug-in replacements fo r LS-TTL devices and can be used to red uce power consumption in existing desig ns. The MM74HCT240 is an inverting buffer and the MM74HCT244 is a non-i.
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