D-Type Flip-Flop. MM74HCT374 Datasheet

MM74HCT374 Flip-Flop. Datasheet pdf. Equivalent

Part MM74HCT374
Description 3-STATE Octal D-Type Latch . 3-STATE Octal D-Type Flip-Flop
Feature MM74HCT373 • MM74HCT374 3-STATE Octal D-Type Latch • 3-STATE Octal D-Type Flip-Flop February 1984 R.
Manufacture Fairchild
Datasheet
Download MM74HCT374 Datasheet

MM74HCT373 • MM74HCT374 3-STATE Octal D-Type Latch • 3-STATE MM74HCT374 Datasheet
MM74HCT374 Datasheet
Recommendation Recommendation Datasheet MM74HCT374 Datasheet




MM74HCT374
February 1984
Revised February 1999
MM74HCT373 • MM74HCT374
3-STATE Octal D-Type Latch •
3-STATE Octal D-Type Flip-Flop
General Description
The MM74HCT373 octal D-type latches and
MM74HCT374 Octal D-type flip flops advanced silicon-
gate CMOS technology, which provides the inherent bene-
fits of low power consumption and wide power supply
range, but are LS-TTL input and output characteristic &
pin-out compatible. The 3-STATE outputs are capable of
driving 15 LS-TTL loads. All inputs are protected from dam-
age due to static discharge by internal diodes to VCC and
ground.
When the MM74HCT373 LATCH ENABLE input is HIGH,
the Q outputs will follow the D inputs. When the LATCH
ENABLE goes LOW, data at the D inputs will be retained at
the outputs until LATCH ENABLE returns HIGH again.
When a high logic level is applied to the OUTPUT CON-
TROL input, all outputs go to a high impedance state,
regardless of what signals are present at the other inputs
and the state of the storage elements.
The MM74HCT374 are positive edge triggered flip-flops.
Data at the D inputs, meeting the setup and hold time
requirements, are transferred to the Q outputs on positive
going transitions of the CLOCK (CK) input. When a high
logic level is applied to the OUTPUT CONTROL (OC)
input, all outputs go to a high impedance state, regardless
of what signals are present at the other inputs and the state
of the storage elements.
MM74HCT devices are intended to interface between TTL
and NMOS components and standard CMOS devices.
These parts are also plug in replacements for LS-TTL
devices and can be used to reduce power consumption in
existing designs.
Features
s TTL input characteristic compatible
s Typical propagation delay: 20 ns
s Low input current: 1 µA maximum
s Low quiescent current: 80 µA maximum
s Compatible with bus-oriented systems
s Output drive capability: 15 LS-TTL loads
Ordering Code:
Order Number Package Number
Package Descriptions
MM74HCT373WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74HCT373SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HCT373MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HCT373N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
MM74HCT373WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74HCT373SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HCT373MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HCT373N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 1999 Fairchild Semiconductor Corporation DS005367.prf
www.fairchildsemi.com



MM74HCT374
Connection Diagrams
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
MM74HCT373
Top View
MM74HCT374
Truth Tables
MM74HCT373
Output
Control
L
L
L
H
LE
H
H
L
X
Data
H
L
X
X
373
Output
H
L
Q0
Z
H = HIGH Level
L = LOW Level
Q0 = Level of output before steady-state input conditions were established.
Z = High Impedance
MM74HCT374
Output
Control
L
L
L
H
Clock
L
X
Data
H
L
X
X
Output
(374)
H
L
Q0
Z
H = HIGH Level
L = LOW Level
X = Don’t Care
↑ = Transition from LOW-to-HIGH
Z = High Impedance State
Q0 = The level of the output before steady state input conditions were
established.
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