MM74HCT74 and Clear Datasheet

MM74HCT74 Datasheet, PDF, Equivalent


Part Number

MM74HCT74

Description

Dual D-Type Flip-Flop with Preset and Clear

Manufacture

Fairchild

Total Page 7 Pages
Datasheet
Download MM74HCT74 Datasheet


MM74HCT74
February 1984
Revised January 1999
MM74HCT74
Dual D-Type Flip-Flop with Preset and Clear
General Description
The MM74HCT74 utilizes advanced silicon-gate CMOS
technology to achieve operation speeds similar to the
equivalent LS-TTL part. It possesses the high noise immu-
nity and low power consumption of standard CMOS inte-
grated circuits, along with the ability to drive 10 LS-TTL
loads.
This flip-flop has independent data, preset, clear, and clock
inputs and Q and Q outputs. The logic level present at the
data input is transferred to the output during the positive-
going transition of the clock pulse. Preset and clear are
independent of the clock and accomplished by a low level
at the appropriate input.
The 74HCT logic family is functionally and pin-out compati-
ble with the standard 74LS logic family. All inputs are pro-
tected from damage due to static discharge by internal
diode clamps to VCC and ground.
MM74HCT devices are intended to interface between TTL
and NMOS components and standard CMOS devices.
These parts are also plug-in replacements for LS-TTL
devices and can be used to reduce power consumption in
existing designs.
Features
s Typical propagation delay: 20 ns
s Low quiescent current: 40 µA maximum (74HCT Series)
s Low input current: 1 µA maximum
s Fanout of 10 LS-TTL loads
s Meta-stable hardened
Ordering Code:
Order Number Package Number
Package Description
MM74HCT74M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
MM74HCT74SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
M74HCT74MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HCT74N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Truth Table
Pin Assignments for DIP, SOIC, SOP and TSSOP
Inputs
Outputs
PR CLR CLK
D
Q
Q
LHXXHL
HLXXLH
L L XXHH
(Note 1) (Note 1)
HH HH L
HHL LH
H H L X Q0 Q0
Q0 = the level of Q before the indicated input conditions were established.
Note 1: This configuration is nonstable; that is, it will not persist when pre-
set and clear inputs return to their inactive (HIGH) level.
© 1999 Fairchild Semiconductor Corporation DS005360.prf
www.fairchildsemi.com

MM74HCT74
Logic Diagram
www.fairchildsemi.com
2


Features MM74HCT74 Dual D-Type Flip-Flop with Pre set and Clear February 1984 Revised Ja nuary 1999 MM74HCT74 Dual D-Type Flip- Flop with Preset and Clear General Desc ription The MM74HCT74 utilizes advanced silicon-gate CMOS technology to achiev e operation speeds similar to the equiv alent LS-TTL part. It possesses the hig h noise immunity and low power consumpt ion of standard CMOS integrated circuit s, along with the ability to drive 10 L S-TTL loads. This flip-flop has indepen dent data, preset, clear, and clock inp uts and Q and Q outputs. The logic leve l present at the data input is transfer red to the output during the positivego ing transition of the clock pulse. Pres et and clear are independent of the clo ck and accomplished by a low level at t he appropriate input. The 74HCT logic f amily is functionally and pin-out compa tible with the standard 74LS logic fami ly. All inputs are protected from damag e due to static discharge by internal d iode clamps to VCC and ground. MM74HCT devices are intended to .
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