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9202 Dataheets PDF



Part Number 9202
Manufacturers STMicroelectronics
Logo STMicroelectronics
Description Flash Programmable System Devices with 8032 Microcontroller Core
Datasheet 9202 Datasheet9202 Datasheet (PDF)

UPSD3254A, UPSD3254BV UPSD3253B, UPSD3253BV Flash Programmable System Devices with 8032 Microcontroller Core FEATURES SUMMARY s The uPSD325X devices combine a Flash PSD architecture with an 8032 microcontroller core. The uPSD325X devices of Flash PSDs feature dual banks of Flash memory, SRAM, general purpose I/O and programmable logic, supervisory functions and access via USB, I2C, ADC, DDC and PWM channels, and an on-board 8032 microcontroller core, with two UARTs, three 16-bit Timer/Counters a.

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UPSD3254A, UPSD3254BV UPSD3253B, UPSD3253BV Flash Programmable System Devices with 8032 Microcontroller Core FEATURES SUMMARY s The uPSD325X devices combine a Flash PSD architecture with an 8032 microcontroller core. The uPSD325X devices of Flash PSDs feature dual banks of Flash memory, SRAM, general purpose I/O and programmable logic, supervisory functions and access via USB, I2C, ADC, DDC and PWM channels, and an on-board 8032 microcontroller core, with two UARTs, three 16-bit Timer/Counters and two External Interrupts. As with other Flash PSD families, the uPSD325X devices are also in-system programmable (ISP) via a JTAG ISP interface. s Large 32KByte SRAM with battery back-up option s Figure 1. 52-lead, Thin, Quad, Flat Package TQFP52 (T) Dual bank Flash memories – 128KByte or 256KByte main Flash memory – 32KByte secondary Flash memory s Content Security – Block access to Flash memory www.DataSheet4U.com Figure 2. 80-lead, Thin, Quad, Flat Package s Programmable Decode PLD for flexible address mapping of all memories within 8032 space. High-speed clock standard 8032 core (12-cycle) USB Interface (some devices only) I2C interface for peripheral connections 5 Pulse Width Modulator (PWM) channels Analog-to-Digital Converter (ADC) Standalone Display Data Channel (DDC) Six I/O ports with up to 46 I/O pins 3000 gate PLD with 16 macrocells Supervisor functions with Watchdog Timer In-System Programming (ISP) via JTAG Zero-Power Technology Single Supply Voltage – 4.5 to 5.5V – 3.0 to 3.6V TQFP80 (U) s s s s s s s s s s s s September 2003 Rev. 1.2 1/175 UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 uPSD325X Devices Product Matrix (Table 1.) . . . . TQFP52 Connections (Figure 3.) . . . . . . . . . . . . . . TQFP80 Connections (Figure 4.) . . . . . . . . . . . . . . 80-Pin Package Pin Description (Table 2.) . . . . . . . ....... ....... ....... ....... ...... ...... ...... ...... . . . . . . . . . . . . . . . . . . . . . . . 13 . . . . . . . . . . . . . . . . . . . . . . . 13 . . . . . . . . . . . . . . . . . . . . . . . 14 . . . . . . . . . . . . . . . . . . . . . . . 15 52 PIN PACKAGE I/O PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 ARCHITECTURE OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Memory Map and Address Space (Figure 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8032 MCU Registers (Figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Configuration of BA 16-bit Registers (Figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Stack Pointer (Figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 PSW (Program Status Word) Register (Figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Interrupt Location of Program Memory (Figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 XRAM-DDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 XRAM-PSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 RAM Address (Table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Addressing Modes . . . . . . . . . . . Direct Addressing (Figure 11.). . . . Indirect Addressing (Figure 12.) . . Indexed Addressing (Figure 13.) . . ....... ....... ....... ....... ...... ...... ...... ...... ....... ....... ....... ....... ...... ...... ...... ...... ....... ....... ....... ....... ...... ...... ...... ...... . . . . . . . . . . 21 . . ..


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