9328 Datasheet: Dual 8-Bit Shift Register





9328 Dual 8-Bit Shift Register Datasheet

Part Number 9328
Description Dual 8-Bit Shift Register
Manufacture National Semiconductor
Total Page 6 Pages
PDF Download Download 9328 Datasheet PDF

Features: 9328 DM9328 Dual 8-Bit Shift Register J une 1989 9328 DM9328 Dual 8-Bit Shift Register General Description The ’932 8 is a high speed serial storage elemen t providing 16 bits of storage in the f orm of two 8-bit registers The multifun ctional capability of this device is pr ovided by several features 1) additiona l gating is provided at the input to bo th shift registers so that the input is easily multiplexed between two sources 2) the clock of each register may be p rovided separately or together 3) both the true and complementary outputs are provided from each 8-bit register and b oth registers may be master cleared fro m a common input Connection Diagram Du al-In-Line Package Logic Symbol TL F 9793 – 1 Order Number 9328DMQB 9328F MQB or DM9328N See NS Package Number J1 6A N16E or W16A TL F 9793 – 2 VCC e Pin 16 GND e Pin 8 Pin Names S D0 D1 C P Description Data Select Input Data I nputs Clock Pulse Input (Active HIGH) C ommon (Pin 9) Separate (Pins 7 and 10) Master Reset Input (Active LOW.

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9328 DM9328 Dual 8-Bit Shift Register
General Description
The ’9328 is a high speed serial storage element providing
16 bits of storage in the form of two 8-bit registers The
multifunctional capability of this device is provided by sever-
al features 1) additional gating is provided at the input to
both shift registers so that the input is easily multiplexed
between two sources 2) the clock of each register may be
provided separately or together 3) both the true and com-
plementary outputs are provided from each 8-bit register
and both registers may be master cleared from a common
input
Connection Diagram
Dual-In-Line Package
Logic Symbol
June 1989
TL F 9793 – 1
Order Number 9328DMQB 9328FMQB or DM9328N
See NS Package Number J16A N16E or W16A
VCC e Pin 16
GND e Pin 8
Pin Names
S
D0 D1
CP
MR
Q7
Q7
Description
Data Select Input
Data Inputs
Clock Pulse Input (Active HIGH)
Common (Pin 9)
Separate (Pins 7 and 10)
Master Reset Input (Active LOW)
Last Stage Output
Complementary Output
TL F 9793 – 2
C1995 National Semiconductor Corporation TL F 9793
RRD-B30M115 Printed in U S A

                 






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