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NT68P62 Dataheets PDF



Part Number NT68P62
Manufacturers ETC
Logo ETC
Description 8-Bit Microcontroller for Monitor (32K OTP ROM Type)
Datasheet NT68P62 DatasheetNT68P62 Datasheet (PDF)

NT68P62-01 8-Bit Microcontroller for Monitor (32K OTP ROM Type) Features n n n n n n n n n n n Operating voltage range: 4.5V to 5.5V CMOS technology for low power consumption 6502 8-bit CMOS CPU core 8 MHz operation frequency 32K bytes of OTP (one time programming) ROM 512 bytes of RAM One 8-bit base timer 13 channels of 8-bit PWM outputs with 5V open drain 4 channel A/D converters with 6-bit resolution 25 bi-directional I/O port pins (8 dedicated I/O pins) Hsync/vsync signals processor for sepa.

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NT68P62-01 8-Bit Microcontroller for Monitor (32K OTP ROM Type) Features n n n n n n n n n n n Operating voltage range: 4.5V to 5.5V CMOS technology for low power consumption 6502 8-bit CMOS CPU core 8 MHz operation frequency 32K bytes of OTP (one time programming) ROM 512 bytes of RAM One 8-bit base timer 13 channels of 8-bit PWM outputs with 5V open drain 4 channel A/D converters with 6-bit resolution 25 bi-directional I/O port pins (8 dedicated I/O pins) Hsync/vsync signals processor for separate & composite signal, including hardware sync signals polarity detection and freq. counters with 2 sets of Hsync counting interval n Hsync/Vsync polarity controlled output, 5 selectable free run output signals and self-test patterns, automute function, half freq. I/O function n Two built-in I2C bus interfaces support VESA DDC1/2B+ n Two layers of interrupt management NMI interrupt sources - INTE0 (External INT with selectable edge trigger) - INTMUTE (Auto Mute Activated) IRQ interrupt sources - INTS0/1 (SCL Go-low INT) - INTA0/1 (Slave Address Matched INT) - INTTX0/1 (Shift Register INT) - INTRX0/1 (Shift Register INT) - INTNAK0/1 (No Acknowledge) - INTSTOP0/1 (Stop Condition Occurred INT) - INTE1 (External INT with Selectable Edge Trigger) - INTV (VSYNC INT) - INTMR (Base Timer INT) - INTADC (AD Conversion Done INT) n Hardware watch-dog timer function n 40-pin P-DIP and 42-pin S-DIP packages General Description The NT68P62 is a new generation of monitor µC for autosync and digital control applications. Particularly, this chip supports various and efficient functions to allow users to easily develop USB monitors. It contains the 6502 8-bit CPU core, 512 bytes of RAM used as working RAM and stack area, 32K bytes of OTP ROM, 13-channel of 8-bit PWM D/A converters, 4-channel A/D converters for keys detection which can save I/O pins, one 8-bit pre-loadable base timer, internal Hsync and Vsync signals processor, and a watch-dog timer which prevents the system from 2C bus interface. The user abnormal operation and two I can store EDID data in the 128 bytes of RAM for DDC1/2B, so that user can reduce a dedicated EEPROM for EDID. And Half frequency output function can save external oneshot circuit. All of these designs are committed to offer our user saving component cost. The 42 pin S-DIP IC provides two additional I/O pins – port40 & port41, Part number NT68P62U represents the S-DIP IC. For future reference, port40 & port42 is only available for the 42 pin S-DIP IC. 1 V2.2 NT68P62-01 Pin Configurations 40-Pin P-DIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSYNCI/INTV [A14] HSYNCI DAC3 [MODE0] DAC4/SCL1 [MODE1] DAC5/SDA1 [MODE2] DAC6 [RESET] CREG P07/HSYNCO [A7] P06/VSYNCO [A6] P05/DAC12 [A5] P04/DAC11 [A4] P03/DAC10 [A3] P02/DAC9 [A2] P01/DAC8 [A1] P00/DAC7 [A0] P31/SCL0 [A13] P30/SDA0 [A12] P20 [DB0] P21 [DB1] P22 [DB2] [PGM] DAC2 DAC1/ADC3 [OE] DAC0/ADC2 [VPP] RESET VDD P40 GND OSCO OSCI P15/INTE0 [CE] P14/PATTERN [A11] P13/HALFI [A10] P12/HALFO [A9] P11/ADC1 [A8] P10/ADC0 P16/INTE1 [DB7] P27 [DB6] P26 [DB5] P25 [DB4] P24 [DB3] P23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VSYNCI/INTV [A14] HSYNCI DAC3 [MODE0] DAC4/SCL1 [MODE1] DAC5/SDA1 [MODE2] P41 DAC6 [RESET] CREG P07/HSYNCO [A7] P06/VSYNCO [A6] P05/DAC12 [A5] P04/DAC11 [A4] P03/DAC10 [A3] P02/DAC9 [A2] P01/DAC8 [A1] P00/DAC7 [A0] P31/SCL0 [A13] P30/SDA0 [A12] P20 [DB0] P21 [DB1] P22 [DB2] [PGM] DAC2 DAC1/ADC3 [OE] DAC0/ADC2 [VPP] RESET VDD GND OSCO OSCI P15/INTE0 [CE] P14/PATTERN [A11] P13/HALFI [A10] P12/HALFO [A9] P11/ADC1 [A8] P10/ADC0 P16/INTE1 [DB7] P27 [DB6] P26 [DB5] P25 [DB4] P24 [DB3] P23 NT68P62U NT68P62 *[ *[ ]: OTP Mode ]: OTP Mode 42-Pin S-DIP Block Diagram VDD CREG GND OSCI OSCO INTE0/1 VSYNCI/INTV HSYNCI Voltage Regulator OTP Program ROM 32K Bytes IIC BUS SCL0 SDA0 SCL1 SDA1 Timing Generator SRAM + STACK 512 Bytes CPU core 6502 A/D Converter 8-Bit Base Timer Interrupt Controller P00 - P07 P10 - P16 H/V Sync Signals Processor Watch Dog Timer I/O Ports P20 - P27 P30 - P31 P40 - P41 PWM DACs DAC0 - DAC7 DAC8 - DAC12 ADC0 - ADC3 VSYNCO HSYNCO PATTERN HALFI HALFO 2 NT68P62-01 Pin Description Pin No. 40 Pin 1 42 Pin 1 Designation DAC2 [ PGM ] 2 3 2 3 DAC1/ADC3 DAC0/ADC2 [ OE ] 4 4 RESET [ VPP ] 5 6 7 8 9 5 7 8 9 10 VDD GND OSCO OSCI P15/INTE0 I [P] P P O I I/O DAC1 DAC0 Reset Init. I/O O [I] O O Description Open drain 5V, D/A converter output 2 [OTP ROM program control] Open drain 5V, D/A converter output 1, shared with A/D converter channel 3 input Open drain 5V, D/A converter output 0, shared with A/D converter channel 2 input [OTP ROM program output enable] Schmitt Trigger input pin, low active reset with internal pulled down 50KΩ register * [OTP ROM program supply voltage] Power Ground Crystal OSC output Crystal OSC input Bi-directional I/O pin with internal pulled up 22KΩ register, shared.


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